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C5515 I2S Frame sync spec timing

Danimal
Expert 1135 points

3 questions:

I'm configuring the C5515 i2s port for slave DSP format mode operation.

1. Is figure 6-29 of the data sheet applicable to the DSP Format Mode of operation of the I2s?

THe figure does not show the pulse as indicated in the figure 1-10 of the I2s user guide (sprufx4). Also notice the I2s_clk and i2s_fs don't appear

to conform to the 6-29 figure where the falling edge of the i2s_fs is after the clock edge.

2. Section 1.2.52 states "With one bit delay, the MSB coincides with the trailing edge of I2Sn_FS" appears to be incorrectly worded.

Does the MSB coincide with the next falling edge of the clock following the trailing edge of the i2sn_fs?

3. In slave mode of operation, since the i2s clock generator is not used (per section 1.2.2 I2S Clock Generator). Is it safe to simply disable the i2s clock generator?

 

 

 

  • 0
    Expert 1135 points

    Here's a screen shot of the I2s2 Protocol frame sync (FS). We are only looking at the receive data path at the moment.

    The I2sSCTRL register is set to 0x08121 to make the protocol work. This setting are for FSPL=0, CLKPOL=0, and DATADLY=1 (Two bit delay), FRMT=1 (DSP mode).   The receive data is sampled on the falling edge of the bit clock.

    You may notice that this figure 1-10 of the SPRUFX4 (C5515 I2s user's guide). That figure describes 1-bit delay operation.

    When I configure the system to use 1 bit delay it simply does not work correctly (everything is essentially bit shifted). 

    Using the figure below as a reference, does the first data bit need to be setup 1 clock earlier to use the DATADLY=0 (1 bit delay) operation ?

     Any other tips?

     

     

  • 0
    TI__Genius 14965 points

    Hi,

    1. Yes

    2. One bit delay is respecting from rising edge of frame sync.

    3. There is no control register to disable I2S Clock Generator. Clock Gate for I2S must be on when you use I2S.

    Regards,

    Hyun