DRA829V: TDA4VM: Testing internal memory (TCM, MSRAM) SECDED protection

Is any information could be provided by TI for the questions above?

1) Yes, ECC aggregator can inject single/double bit error to the ECC protected memory.

2) No

3) No

4)

For TCM ECC, please refer to ARM Cortex R5 document. Depending on the configuration, TCM can correct 1-bit error and write it back to TCM. Or, it can be disabled and generate abort instead.

https://developer.arm.com/documentation/ddi0460/d/Level-One-Memory-System/About-the-TCMs/TCM-internal-error-detection-and-correction?lang=en

For MSRAM, SECDED does correct 1-bit error in memory.

5) Yes for MSMC and DDR.

Hi Stanley,

thanks for your answer. Could you please make some additional clarifications.

- Regarding p.1: I've talked to a colleague of mine, who worked with ECC aggregators. Our understanding is that injection of an error by ECC is not a 'real' fault injection into a memory, rather forcing error reaction by ECC aggregator itself. Could you please confirm or refute it.
If it is not a 'real' fault injection into the memory, can we force such? For example I worked in past with Hercules MCU and for TCM it was possible to disable ECC, unlock writing to ECC area and corrupt it, enable ECC, perform reading and observe reaction, so the whole path is involved.  

- Regarding p.4: ARM documentation is a bit vague, from my point of view. It says that 'the processor normally generates the correct data and writes it back to the TCM'. This 'normally' sounds a bit confusing, don't you know when this 'normally' does not happen?

Thanks for your help,
Dmitry

Hi Stanley,

could you give more information regarding clarification above.

Thanks,
Dmitry

Hi,

is there any updates regarding the questions above?