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TDA4VM: Questions about CPTS and GTS in time synchronization

Albert
Prodigy 210 points
Part Number: TDA4VM


Hi， TI experts

I have some questions about the use of CPTS and GTS

1.  mcu_2_0 can control CPTS. Can it synchronize time by communicating with the ptp server directly through the internal switch

2. Can GTC be accessed by all cores, and if so, can mcu_2_0 modify the GTC time directly after synchronizing CPTS to achieve inter-core synchronization

3. CPTS can already be used as a time base, why do you need a GTC to be used as a global time base

  • 0
    Prodigy 210 points

    Hi, TI experts

    I have another question, can A72 directly control CPTS?

  • +1
    TI__Mastermind 39580 points

    Hi,

    On TDA4VM, we have normal CPTS as well as CPTS which are part of CPSW (ethernet switch). This is regarding the CPTS which are part of CPSW. Let me know if this isn't what you are asking. Btw, the other CPTS do not have PTP support.

    Albert said:

    1.  mcu_2_0 can control CPTS. Can it synchronize time by communicating with the ptp server directly through the internal switch

    If you are using ethfw, mcu2_0 controls the CPSW9G and hence controls CPTS. We currently have a validation purpose PTP stack on ethfw which is meant for testing and not for production purpose. But, if you include a PTP stack, you can communicate with a PTP server and sync the CPSW9G CPTS clock to master clock. But it will not alter the SYSTEM_TIME which is actually used to measure times across cores. But even without ethfw, you can use the MCU_CPSW2G from linux to do the same.

    Albert said:

    2. Can GTC be accessed by all cores, and if so, can mcu_2_0 modify the GTC time directly after synchronizing CPTS to achieve inter-core synchronization

    Yes, this should be possible.

    Albert said:
    3. CPTS can already be used as a time base, why do you need a GTC to be used as a global time base

    As there are multiple CPTS clocks on board, we need a common system time across SoC where a GTC comes into picture.

    Albert said:
    can A72 directly control CPTS?

    It can. The MCU_CPSW2G is controlled using A72, the CPTS it has can be controlled from A72 using linux tools such as ptp4l, phc2sys etc. If you want to control the CPTS associated with CPSW9G, you can do that if you use native linux driver for CPSW9G.

    Regards,
    Tanmay

  • 0 in reply to Tanmay Patil
    Prodigy 210 points

    Hi,

    I want to synchronize CPTS by pps+tod, can pps connect to mcu2_0?

    thanks

  • 0 in reply to Albert
    TI__Mastermind 39580 points

    Hi,

    I am not aware what pps or tod is. Can you elaborate? From you question it seems like some device hence I am confused.

    Regards,
    Tanmay

  • 0 in reply to Tanmay Patil
    Prodigy 210 points

    Hi,

    For example, GNSS timing, a one-second pulse, adjusts milliseconds, microseconds, and nanoseconds to zero, and a GPRMC message, gets the year, month, day, hour, minute, second. The pulse is PPS, GPRMC is TOD, and then I thought mcu2_0 could process that information to synchronize CPTS, or maybe sync CPTS directly on A72?

  • +1 in reply to Albert
    TI__Mastermind 39580 points

    Hi,

    As the GNSS and GPRMC doesn't come under the scope of our driver, we don't have the support to use them.

    What we do have is a PTP stack on linux which can sync-up the ptp hardware clock with a master clock and then sync the system clock with the ptp hardware clock. This can happen in reverse as well with ptp hardware clock synced-up with system clock and then a slave clock synced-up over ptp with the on-board ptp hardware clock. Currently, this is all possible on A72.

    I am not aware how the pps+tod is processed to get the time.

    Hope this clarifies your doubt.

    Regards,
    Tanmay