TDA4VM: I have some questions about CPTS

Hi Liang,

Can you please confirm that the CPTS you want to enquire is the CPTS in CPSW module or other CPTS.

Regards,
Tanmay

Hi Tanmay,

I am asking about CPTS in CPSW for PTP time synchronization.

I think if all cores can get the time of CPTS through HW_PUSH, there is no need to synchronize the time between cores through GTC

Regards,
Liang

Hi Tanmay,

I have another question

Is the time synchronized with the phc2sys tool to CPTS in CPSW2G?

Do CPSW2G and CPSW9G operate the same CPTS?

Regards,
Liang

Hi Liang,

Albert said:

 In SDK8.5 version A core can directly access CPTS, I would like to ask if SDK7.3 version A core can also directly access CPTS

We have two different CPTS for CPSW2G and CPSW9G. On SDK 7.3, A core can access CPTS of CPSW2G but not of CPSW9G. Its possible to control both CPTS in SDK 8.5.

Albert said:

Is the time synchronized with the phc2sys tool to CPTS in CPSW2G?

phc2sys is used to sync time between the system clock (GTC) and the CPTS clock. It can be done in CPSW2G.

Albert said:

 I saw in the chip manual that CPTS supports 8 HW_TS_PUSH events. I would like to ask whether each core can occupy one event to directly obtain the CPTS time through this function. Are there any PUSH events that have been assigned by SDK8.5 and cannot be used?

I am working on getting answers for this. I will update you on this by the end of this week.

Sorry for the delay.

Regards,
Tanmay

Hi Tanmay,

In sdk8.5 A core can control CPTS in CPSW9G. which A  core can process gptp messages through CPSW9G, and how do I route the messages for processing?

if A core uses CPTS in CPSW2G to synchronize gptp, can GTC establish a linear relationship with CPTS in CPSW2G? How do I configure it

In SDK7.3, I used phc2sys to synchronize CPTS to the system clock in core A and r5_2_0 printed the GTC value unchanged. Is there more than one GTC? Or will SDK8.5 change the value of GTC?

Finally, in the linear relationship between GTC and CPTS, what if GTC is Inaccurate?

Thank you for your answer.

Regards,
Liang

Hi Liang,

Albert said:

In sdk8.5 A core can control CPTS in CPSW9G. which A  core can process gptp messages through CPSW9G, and how do I route the messages for processing?

We use ptp4l for testing ptp on A72. Linux running on A72 has a ptp stack, so you don't need to route the messages.

Albert said:

if A core uses CPTS in CPSW2G to synchronize gptp, can GTC establish a linear relationship with CPTS in CPSW2G? How do I configure it

I just found out that the synchronization using phc2sys might not get translated to GTC being updated. I am checking up on this for a more detailed answer.

I will get back to you within a week.

Regards,
Tanmay

Hi Tanmay,

   I control CPTS through native driver, but there are several CPTS. How do I determine which CPTS I control through native driver

Thank you for your answer.

Regards,
Liang

Hi Tanmay,

I've found a way to make sure.

However, there is a new problem, which is how I can synchronize between cores in native driver mode. The linear relationship between GTC and CPTS requires the configuration of GTC and TSR. Can I configure it under core A? And how do I get the timestamp of the HW_PUSH event that GTC sent to CPTS in core A

Regards,
Liang