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Combining NDK and UPP driver projects

Mitch Nelson
Expert 1440 points

Attached is a zip with two projects, a working NDK project and a working UPP project.  (They are both TI examples)

I need to combines these into one project.

Can the TCF files be merged by simple copy and paste?

Are there conflicts?  If so, how can they be resolved? 

2526.twoprojects.zip

 

Thank you,

Mitch Nelson

  • 0
    TI__Mastermind 45025 points

    Mitch,

    I see that each file imports a tci file - "uppSample.tci" and "ndk.tci".  Since I don't know the contents of those, I'm assuming there's nothing conflicting in those files ...

    Having said that, looking at just these tcf files I see that there are some conflicts.

    First, I see that each one creates a heap in DDR.  There can only be one heap in DDR, so you should decide whether you want it to be 0x40000 or 0x00010000.

    Your DVTEvent log has different buf sizes.

    You've changed the size of IRAM in preprocessor.tcf; this may affect uppsample.

    I also see the following is only in preprocessor.tcf

    ios.setMemDataHeapSections(prog, prog.get("DDR"));
    bios.setMemDataNoHeapSections(prog, prog.get("DDR"));

     

    The general idea is to compare the 2 and see what the differences are.  Then, for each difference, decide if you need it in your "combo" app or not.

     

    Steve

     

  • 0 in reply to Steven Connell
    Expert 1440 points

    Re the IRAM, are we talking about the following (from preprocessor)?

    /* MAR bits config */

    bios.GBL.C64PLUSMAR128to159 = 0x0000ffff;

    //bios.GBL.C64PLUSL2CFG = "256k";

    What should it be?

    (the preprocessor file is actually as shipped in the nsp)

    Thank you

    Mitch

  • 0 in reply to Mitch Nelson
    TI__Mastermind 45025 points

    Mitch,

    I'm referring to this statement:

    /* Board specific settings */
    bios.MEM.instance("IRAM").len = 0x0002ffff;

    The following statement is to enable parts of external memory for caching:

    /* MAR bits config */
    bios.GBL.C64PLUSMAR128to159 = 0x0000ffff;

    The MAR register is used to specify memory ranges that should be cacheable.  Here's an example from an email I wrote a while back:

    The above settings such as C64PLUSMAR192to223 are used to configure the DSP’s MAR registers.  The MAR registers are used to make specific ranges of memory cacheable, or non-cacheable.  Each bit in the range specified by the name corresponds to a MAR register bit. Each of these MAR bits then corresponds to a particular range of memory.

     

    So, for example, for Cache.MAR192_223 = 0x8 this corresponds to bit number 195 of that MAR register.

     

    MAR 192 – 223 = 0x8:

     

    1| 1 | 1 | 1|        | 2

    9| 9 | 9 | 9| …   | 2

    2| 3 | 4 | 5|        | 3

    -----------------------

    0 | 0 | 0 | 1 | … | 0

     

    Bit 195 corresponds to the memory range 0xc300 0000 – 0x C3FFFFFF and setting this bit to one will make that range of memory cacheable.

     

    Note that for the evmDA830 (BIOS6 case) the range:

     

    0xc300 0000 – 0x C3FFFFFF

     

    Is the entire external memory segment SDRAM.  However, for evm6747 (BIOS5 case) external memory is larger and has the range:

     

    0xc000 0000 – 0x C3FFFFFF

     

    So, setting the MAR192to223 to 0x8 only made the last quarter of the external memory cacheable for the BIOS5 case.  Setting the MAR192to223 = 0xF enables bits 192, 193, 194, and 195 and so covers the entire external memory range 0xc000 0000 – 0x C3FFFFFF for the evm6747 case:

     

    MAR 192 – 223 = 0xF:

     

    1| 1 | 1 | 1|        | 2

    9| 9 | 9 | 9| …   | 2

    2| 3 | 4 | 5|        | 3

    -----------------------

    1 | 1 | 1 | 1 | … | 0

     

     

    Hope this helped …

     

    Steve