AM6412: AM6412 3-PORT SWITCH and PRU

Hello Alex,

1) To confirm, are you specifically looking for switch functionality, where Ethernet packets from one Ethernet interface can be passed at the hardware level on to the other Ethernet interface? Or are you just looking for two separate Ethernet MAC interfaces?

2) To confirm, do you want all the Ethernet interfaces controlled from the Linux A53 cores, or did you want one of the interfaces managed by another core, like the RTOS R5F cores?

The CPSW can be run in dual EMAC mode (i.e., the Ethernet ports are unrelated), or in switch mode. More information here: https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/08_05_00_21/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW3g.html 

Regards,

Nick

Hello,

1) I am looking for 2 separate ETH MAC Interfaces

2) I cannot confirm at this stage if only A53 will control these 2 interfaces. Can you explain further or suggest ?

3) Dual MAC seems the app for my case. Briefly reading the link I can understand that only one (ETH0) port is up at Linux....not 2 (Ideally 2 ports will be needed).

    Additionally , the 2nd port is emulated using VLANs....have I got it right ? 

    So these 2 separate external ports , will have 2 different IPs , 2 different MAC addresses...but wont be seen from linux as 2 port entities...but as one.

Thanks

Alex

Hello,

As far as the PRU module , I understand that this block contains 2 x 10/100/1000 eth ports.

Can any of these ports be used as a standard ethernet interface..so that I can achieve using 2 eth interfaces ? (eth0 and eth1 ) 

Thanks

Alex

Hello Alex,

CPSW 

CPSW can present two separate Ethernet MAC interfaces. Two separate PHY interfaces, that Linux treats as two separate Ethernet instances. E.g., you can have an IP address 192.168.1.100 on one Ethernet port, and then the other Ethernet port can be on a totally different network and subnet, like 192.168.2.160.

So Linux sees the CPSW interfaces as totally separate. No tricky VLAN emulation or anything like that is needed. So where does the "3rd port" come in?

Each of the Ethernet PHYs is a gigabit ethernet port, so that is 2 ports. And then there is a third gigabit port coming out of the CPSW towards Linux. So this means that even through you can connect two gigabit interfaces to external devices, the CPSW is bottlenecked to about a gigabit coming from the CPSW to the core it is interfacing with. Keep in mind that the traffic going through might not be symmetric between the two ports. (e.g., if the traffic between both ports exceeds a gigabit, then maybe you'll get 500Mbit throughput on each interface, but you may get something different).

So it sounds like CPSW would be a good fit for your usecase, unless you need both ports to be transferring data at gigabit rates at the same time.

PRU Ethernet 

Yes, this can also be used as a standard Ethernet interface. However, in general I would suggest using CPSW first, since the PRU_ICSSG cores can then be freed up to do other things if your design needs it. I'll let you reply before saying anything else.

Regards,

Nick

Hello Nick,

Thanks for the swift reply.

Very helpful information.

So to sum up :

The 2 external ports can be considered as 2 completely separate ports (Linux) 

3rd port is shared between the 2 ports [ So there is an internal mechanism to detect traffic between the 2 external ports..right ?]

Is this driver available ? Is there any extra cost for this separate port support ?

Is there any mechanism to prevent drops when the 2 ports send traffic at the same time (leading to a 2 x theoretical max of interface instantaneously)

In any case , one of our interfaces can operate in RMII mode if needed...to prevent issues. This interface usually wont go more than 50Mbps..

Thanks

Alex

Hello Alex,

The internal "third port" 

As long as you know that the total throughput between Linux and the two CPSW ports will not go above 1Gbit, you do not need to think about that internal third port. From a programming standpoint, the Linux driver does all the work, and your code will just see two completely separate external ports.

Other questions, including whether the different CPSW ports can run different interfaces (e.g., RGMII on one, RMII on the other) 

I am reassigning your thread to our CPSW expert to comment.

Regards,

Nick

One final note on PRU Ethernet: I just realized you were asking about AM6412. Please note that AM6412 and AM6411 have PRU_ICSSG subsystems like the other AM64x devices. HOWEVER, these subsystems can only be used for non-Ethernet usecases (an example of a supported usecase is bitbanging a custom SPI protocol to control an array of external ADCs).

So if you wanted an AM64x device with PRU_ICSSG Ethernet support, you would need to pick one of the other AM64x part numbers with "PRU_ICSSG Industrial Communication Support" (see datasheet table "Device Comparison"), and make sure the orderable part number includes a feature code of D, E, or F, as per the note below the "Device Comparison" table, and the "Nomenclature Description" table information.

Regards,

Nick

Hello Nick ,

Coming back to my latest comment , I need some further help...

From the CPSW , I am planning to select RGMII1 (PRG0_PRU1 and few from PRG1_PRU1) and RMII2 mode (PRG1_PRU1)...but I have conflict reported...relative to the REFCLK of RMII and RGMII1 TXC...

Can you provide some help on this ? Should I use the CLKOUT0 out pin for RMII 50MHz REFCLK ?

Thanks

Alex

Hi, 

I will need to bring in another colleague who has more expertise on the question that you are asking. This will take a day or two before we can respond.

Best Regards,

Schuyler

Alex,

after 30 days of Inactivity the Thread gets auto Locked. Please open a new thread for additional questions. I am closing this thread.

Regards

Anshu