DM3730: Schematic & layout guidance document of DM3730

Madhurya

I was unable to find any guidelines specific to the DM3730 GPMC interface. However I did find the following that you may find useful. 

GPMC[edit]

• check to make sure any pullups for WAIT signals are 1.8V
• if used, ensure GPMC_CLK has 33ohm series resistor placed close to AM/DM37x

In addition, there are some good details in the follwoing application note that you may also find helpful.

High-Speed Interface Layout Guidelines (Rev. J)

--Paul

Hi Paul!

Thanks for sharing this!

For our now-used CPU platform, there is not much guidance for the GPMC bus. Are there any other documents about GPMC BUS usage, I believe another platform is ok, just need more info here.

Below is the topology of our current design, for now, they want to know the GPMC BUS stub line length / the total length limit, the Parasitic capacitance requirements, which is critical for our design, the maximum number of peripheral devices that are supported.

 Best Regards,

Madhurya

Madhurya

I am checking to see if we can provide further guidance. 

--Paul;

Hi Paul!

Any update?

Best Regards,

Madhurya

Hi Paul!

Do you have any bootloader tool or resource to share along with the above info?

Best Regards,

Madhurya

Hi Madhurya,

Sorry there is no such a document.

The datasheet shows that the timings apply with typical capacitive loading of 12pF - See Table 6-2. GPMC/NOR Flash Timing Conditions—Synchronous Mode
https://www.ti.com/lit/gpn/dm3730

For trace lengths, need to perform timing analysis. Perhaps the IBIS model could be used to simulate with the 4 loads and stubs. A 3D extraction of the board would provide best results. Clock buffering may be required like a 1 to 4 buffer.

Is this design using synchronous or asynch mode? How fast or slow does the system operate?

Regards,
Mark