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TDA4VL-Q1: ddr size changed,whether the memery map need to change?

lify
Intellectual 290 points
Part Number: TDA4VL-Q1

hi TI

     We use SDK j721e-S2 8.04,   our board DDR is 4G(onlu one DDR),but the default DDR setting  in SDK is 16G,  i change the file in linux as following:

   Whether memery map need to change?if need, how to modify?(I didn't modify the memery map.And  i have met some strange problems, i don't kown if it is related to this)

/linux-sdk / board-support/u-boot/arch/arm/dts/k3-j721s2-som-p0.dtsi

{
memory@80000000 {
device_type = "memory";
/* 16 GB RAM->4GB */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x00 0x80000000>;// default is  <0x08 0x80000000 0x03 0x80000000>;
};

board-support/u-boot/board/ti/j721s2/evm.c

#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].size = 0x7fffffff;  //default is 0x37fffffff;
gd->ram_size = 0x100000000;  //default is 0x400000000
#endif

  • 0
    TI__Guru**** 163650 points

    Hi,

    There are more changes that are needed to change the DDR size to 4GB on J721s2 are there are 2 memory controllers.

    Could you please share the patch that you have already created?

    Best Regards,
    Keerthy

  • 0 in reply to Keerthy J
    Intellectual 290 points

    hi Keerthy

      The patch is as following, and our board has only one DDR.

    diff --git a/board-support/u-boot/arch/arm/dts/k3-j721s2-som-p0.dtsi b/board-support/u-boot/arch/arm/dts/k3-j721s2-som-p0.dtsi
    old mode 100644
    new mode 100755
    index f3080e948..a169c63b5
    --- a/board-support/u-boot/arch/arm/dts/k3-j721s2-som-p0.dtsi
    +++ b/board-support/u-boot/arch/arm/dts/k3-j721s2-som-p0.dtsi
    @@ -13,9 +13,9 @@
    / {
    memory@80000000 {
    device_type = "memory";
    - /* 16 GB RAM */
    + /* 16 GB RAM->4GB */
    reg = <0x00 0x80000000 0x00 0x80000000>,
    - <0x08 0x80000000 0x03 0x80000000>;
    + <0x08 0x80000000 0x00 0x80000000>;
    };

    /* Reserving memory regions still pending */
    diff --git a/board-support/u-boot/board/ti/j721s2/evm.c b/board-support/u-boot/board/ti/j721s2/evm.c
    old mode 100644
    new mode 100755
    index 90b7ca115..51e50fa9c
    --- a/board-support/u-boot/board/ti/j721s2/evm.c
    +++ b/board-support/u-boot/board/ti/j721s2/evm.c
    @@ -67,8 +67,8 @@ int dram_init_banksize(void)
    #ifdef CONFIG_PHYS_64BIT
    /* Bank 1 declares the memory available in the DDR high region */
    gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
    - gd->bd->bi_dram[1].size = 0x37fffffff;
    - gd->ram_size = 0x400000000;
    + gd->bd->bi_dram[1].size = 0x7fffffff;
    + gd->ram_size = 0x100000000;
    #endif

    return 0;

  • 0 in reply to lify
    TI__Guru**** 163650 points

    Hi,

    I am able to boot with 4 GB with the below patch on top of Latest 8.5 SDK U-boot repository:

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_Reduce_2D00_DDR_2D00_size_2D00_for_2D00_j721s2_2D00_to_2D00_4GB.patch

    Here is the boot log:

    U-Boot SPL 2021.01-dirty (Mar 07 2023 - 13:25:10 +0530)
    ti_sci system-controller@44083000: Message not acknowledgedSYSFW ABI: 3.1 (firmware rev 0x0008 '8.5.2--v08.05.02 (Chill Capybar')
    SPL initial stack usage: 13472 bytes
    Trying to boot from MMC2
    Starting ATF on ARM64 core...

    NOTICE:  BL31: v2.7(release):v2.7.0-359-g1309c6c805-dirty
    NOTICE:  BL31: Built : 07:48:35, Dec 16 2022
    I/TC:
    I/TC: OP-TEE version: 3.20.0-rc1-18-g8e74d476-dev (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #4 Mon Jan 23 11:06:25 UTC 2023 aarch64
    I/TC: WARNING: This OP-TEE configuration might be insecure!
    I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
    I/TC: Primary CPU initializing
    I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.5.2--v08.05.02 (Chill Capybar')
    I/TC: HUK Initialized
    I/TC: Activated SA2UL device
    I/TC: Fixing SA2UL firewall owner for GP device
    I/TC: Enabled firewalls for SA2UL TRNG device
    I/TC: SA2UL TRNG initialized
    I/TC: SA2UL Drivers initialized
    I/TC: Primary CPU switching to normal world boot

    U-Boot SPL 2021.01-dirty (Mar 07 2023 - 13:25:04 +0530)
    ti_sci system-controller@44083000: Message not acknowledgedSYSFW ABI: 3.1 (firmware rev 0x0008 '8.5.2--v08.05.02 (Chill Capybar')
    Trying to boot from MMC2


    U-Boot 2021.01-dirty (Mar 07 2023 - 13:25:04 +0530)

    SoC:   J721S2 SR1.0 GP
    Model: Texas Instruments J721S2 EVM
    ti_i2c_eeprom_am6_get: Ignoring record id 255
    ti_i2c_eeprom_am6_get: Ignoring record id 255
    ti_i2c_eeprom_am6_get: Ignoring record id 255
    ti_i2c_eeprom_am6_get: Ignoring record id 255
    ti_i2c_eeprom_am6_get: Ignoring record id 255
    ti_i2c_eeprom_am6_get: Ignoring record id 255
    ti_i2c_eeprom_am6_get: Ignoring record id 255
    ti_i2c_eeprom_am6_get: Ignoring record id 255
    ti_i2c_eeprom_am6_get: Ignoring record id 255
    ti_i2c_eeprom_am6_get: Ignoring record id 255
    Board:  rev
    DRAM:  4 GiB
    Flash: 0 Bytes
    MMC:   mmc@4f80000: 0, mmc@4fb0000: 1
    Loading Environment from MMC... *** Warning - bad CRC, using default environment

    In:    serial@2880000
    Out:   serial@2880000
    Err:   serial@2880000
    am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
    Unidentified board claims  in eeprom header
    Net:   eth0: ethernet@46000000port@1
    Hit any key to stop autoboot:  0

    Linux 'free' command output:

    root@j721s2-evm:~# free
                  total        used        free      shared  buff/cache   available
    Mem:        3847044       82560     3643968        9896      120516     3623832
    Swap:             0           0           0

    Let me know if you can boot with the above patch with 4GB DDR. If not we will need to see if your DDR part is different compared to TI EVM
    & then change the ddr dts file accordingly.

    Best Regards,
    Keerthy