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bandwidth on EMIFA bus

Bhupesh Patil
Intellectual 440 points

How much bandwidth can be achieved on EMIFA bus? In the circuit FPGA is connected with DSP. DSP read data from FPGA and writes back to FPGA. The EMIFA bus read and write  cycles are programmed with 39 cycles approximately. With this E=6.73 ns cycle time, I am expecting about 2 MHz, Not able to achieve

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    Genius 3575 points

    Maybe you should give the forum all the relevant information, like the part number of your device.  If you want someone to help you track down your specific problem, you should add more information, like the actual register values used to program the EMIFA bus and what speed you are actually achieving.