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C6678 DDR3 Track Impedances

Richard Marsh
Intellectual 760 points

 

Hi,

 

I cannot find track impedances mentioned in the "DDR3 Design Requirements for Keystone Devices sparabi1a" doc, so thought it worth clarifying.

 

Can you please confirm the following:

 

  • DQS/DQS#  100ohms differential
  • DDR3CLKOUT/DDR3CLKOUT# 100ohms differential
  • All other signals 50ohms single ended

 

Many thanks,

 

Richard

  • 0
    TI__Mastermind 42545 points

    The differential signals should be 100ohm differential.  The impedance of the single ended tracks should be matched but they can all be implemented at a value higher then 50 ohms.  Ideally the impedance should be between 50 and 60 ohms and the impedance a the signal ended signal should the same as the impedance of all the other single ended signals.