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YCbCr with separate syncs capture by CCDC of DM6437

Saira
Intellectual 565 points
Other Parts Discussed in Thread: TVP5146

hi all

 

Can anyone please tell how to configure CCDC of DM6437 to receive YCbCr 8 bit with separate syncs from decoder tvp5146 ????

When I disable embedded syncs of decoder tvp5146 to enable YCbCr with separate syncs than CCDC is not going to capture this......How this can be done ??

 

Plz help

Regards

  • 0
    TI__Expert 4685 points

    Are you trying to use any demo/sample applications or you are working with your own applications? Please provide details for better understanding.

  • 0
    TI__Intellectual 995 points

    You'd need to disable embedded sync on DM6437 CCDC as well. This can be done by setting REC656IF = 0. If you still encounter problems, please use Logic analyzer of oscilloscope to make sure pixel clock, v-sync and h-sync signals are all correct.

    Xiangdong

     

  • 0 in reply to Xiangdong Fu
    Intellectual 565 points

    I am using my own application for capturing in CCDC 8 bit video with separate syncs coming from decoder.

     

    I have done these settings for the decoder

    PSP_VPFE_TVP5146_ConfigParams tvp5146Params = {

    DISABLE_SYNC_656,

    PSP_VPFE_TVP5146_FORMAT_COMPOSITE,

    PSP_VPFE_TVP5146_MODE_AUTO

    };

     

    In file tvp5146_extDecoder.c register settings for seperate syncs are:

    OUTPUT_FORMATTER_2_REG = 0x11;

    LUMINANCE_PROCESSING_CONTROL_1_REG = 0x00;

    LUMINANCE_PROCESSING_CONTROL_3_REG = 0x00;

    CHROMINANCE_PROCESSING_CONTROL_2_REG = 0x04;

    OUTPUT_FORMATTER_1_REG = 0x43;

    OUTPUT_FORMATTER_4_REG = 0xAF;

    SYNC_CONTROL_REG = 0x00;

     

    Now for CCDC

    PSP_VPFECcdcConfigParams vpfeCcdcConfigParams = {

    FVID_CCDC_YCBCR_8,

    FVID_FRAME_MODE,

    480U,

    720U,

    ( 720U * (16 / 8 )),

    0U,

    0U,

    NULL,

    {

               PSP_VPFE_TVP5146_Open,

               PSP_VPFE_TVP5146_Close,

               PSP_VPFE_TVP5146_Control,

    },

    0,

    };

     

    In ddc_vpfeCcdc.c I have changed code under FVID_CCDC_YCBCR_8 input mode if() condition to disable embedded syncs by replacing LLC_setREC656InterfaceEnable() function to LLC_setREC656InterfaceDisable()

    How to set HSYNC and VSYNC and other necessary signals like Field and Pixel Clock etc for CCDC ???

    And kindly inform about any mistakes in this code also ?