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PCIe Clocking of C6678

Richard Marsh
Intellectual 760 points

Hi,

 

As far as I can see the DSP PCIE_CLKp/n input pins are not HSCL compliant, despite this being the dominant clocking scheme in PCIe systems.  

 

What termination scheme does TI recommend for interfacing a HSCL PCIe clock to the PCIE_CLKp/n pins?

 

The errata for the C6678 EVM says that the PCIe clocking will be redesigned for HSCL, so we can't copy the EVM circuitry yet.

 

Many thanks,

 

Richard

  • 0
    TI__Mastermind 42545 points

    The specification for the REFCLK is defined in the PCIe Card Electromechanical Specification Rev 2.0.  According to this specification the voltage levels of the REFCLK at the destination are defined as a minimum of 150mV for VIH and a maximum of -150mV for VIL for a minimum peak-to-peak voltage level of 300mV.  The Low Jitter Clock Buffer in the C6678 is designed as a differential clock input buffer with a wide range to accommodate multiple transmission standards.  The LJCB can accommodate differential clock inputs with peak-to-peak voltages down to 250mV so it will operate correctly with the REFCLK as defined by the PCIe standard.  Note that the LJCB has an internal 100ohm termination across the differential clock inputs and that the clock signal must be AC coupled for proper operation.  The value of the AC coupling capacitor should be selected so that the RC corner frequency is at least two decades below the 100MHz REFCLK frequency. 

    The EVM was originally designed to allow the PCIE_CLK to be either the output of the clock generator or the REFCLK from the edge connector.  Selection between the two required a physical modification to the board.  The production version of the EVM will include a mux that can select between these two clocks.  The mux can also accommodate either the LVDS from the clock generator or the HSCL standard from the edge connector. 

  • 0 in reply to Bill Taboada
    Intellectual 760 points

    Hi Bill,

    It sounds like you're saying that the standard PCIe HSCL clock should work correctly with the LJCB as long as it is AC coupled.  Yet the 'issues' doc for the TMDXEVM6678L seems to imply the opposite:

    "2.3  No HCSL support of the PCIE‐CLK from the AMC FCLK on the EVMs 

    The PCIe clock circuitry does not support HCSL clock from AMC FCLK on Beta1 and Beta2 EVMs. Do NOT try to install the DC‐blocking to provide a PCIe clock from the AMC edge connector. "

    Is there any word on the IBIS file, so that I can simulate this?

    Cheers,

    Rich

  • 0 in reply to Richard Marsh
    TI__Mastermind 42545 points

    The LJCB was developed as a general purpose, wide range differential clock input but it was specifically targeted at  D PECL and LVDS.  Since the use of HCSL clock is limited to the EMC specification for PCIE it was obscure enough that the buffer designers hadn't included it as a supported standard.  Once it became clear that the use of the PCIE REFCLK from the back plane was required we passed the specification information to the LJCB designers for their review.  They responded that a clock meeting thatspecification at the input to the LJCB is compatible with the buffer as long as it is AC coupled. Since the documentation for the Beta1 and Beta2 EVMs is, in fact, beta it was not updated.  As I stated above the production version of the EVM will include a mux allowing the user to select either the HCSL clock from the edge connector or the output of the clock generator to support both backplane and stand alone operation.

  • 0 in reply to Bill Taboada
    Prodigy 235 points

    Regarding driving the LJCB buffers with an HCLS clock driver... Is DC biasing required after the AC coupling in order to get the signals to the right voltage levels, or are the buffers self-biased. If DC biasing is required, then can TI provide a recommended termination scheme for HCSL-to-LJCB?

    Thank you.

  • 0 in reply to Courtney Cooley
    TI__Mastermind 42545 points

    The buffers are self-biased and for HCSL-to-LJCB no terminating resistors after the AC caps should be necessary.