DM8148 DDR3 controller interface

Hello Manoj,

Yes, you can use 2 16-bit DDR3 memory for each bank.  We are not aware of any disadvantage by doing this.

Additional comment from our designer:

"Apart from component cost (which could be higher for 2x16 configuration) there is no disadvantage in using 2x16 vs 4x8.

16x2 does help in having smaller footprint (on board) compared to 4x8 - which could be BOM saving."

Hello Viet,

When we use 2X16, need we modiy the EVM software?

If we need modify of the code, could you tell me which code we need modify?

Thanks.

Yanbin Yue

Yanbin,

You need to modify the DDR configuration.  Please follow the DDR3 user guide in TRM.

Regards,

Viet

Hi Viet，

Where can I find the user guide? What is the TRM means?

I could find all the docs about 8148 as following image :

Thanks,

Yanbin Yue

TRM means "TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual"

http://www.ti.com/lit/ug/sprugz8/sprugz8.pdf

Regards,

Michael

Hi Manoj,

We are also working with a dm8148 connected to DDR3 16 bit memories.

DDR0 connected to two DDR3 memories of width 16bit

DDR1 connected to two DDR3 memories of width 16bit

the DDR3 interface  is not working properly using the configuration of the DM8148 PG2.1.

1/ First, Do you have successfully make this interface working with 16bit DDR3 memory.

2/ If yes, can you share with us your EMIF configurations

thanks a lot for your help,

Hi Jonathan,

Incidentally due to some changed development priorities we are going a little slow on this development. We are yet to finalise full scheme and order the protos for evaluation. Now that this issue has come into picture, I would be eager to know/follow-up the updates .

Thanks

Jonathan,

Please review the DDR3 section in TRM.

BR,

Viet

Hi Viet,

We are about to start testing a new board, based on DM8148 CYE1 operating at OPP166 (533MHz DDR3 interfaces).

Q1 : The TI814x DDR3-init-U-Boot link (http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot) , the file « DDR3_slave_ratio_search_TI814x.out » must be used during the sequence, mainly for write leveling.  Will this .OUT file work for DDR3-1066 (533MHz clock at OP166), or shall we we use a different .OUT file ?

Q2 : If I'm correct, before we use above software, we need to adjust DDR3 PHY to 533MHz. Is there a DDR3 PHY calculation spreasheet for 814X devices, like the one available for DM816x (http://processors.wiki.ti.com/index.php/File:C6A8168_DDR_register_caculate_sheet_V1.1.zip) ?

Thanks in advance for your support.

Dears,

We ar now continuing our development efforts for DM8148 based design. Now that some of you might already have tried it, I want to refresh my question:

Has anybody already realised 16-bit DDR3 interface with DM8148?

Thanks

Manoj,

Yes, we go have some customers use 16-bits DDR3 interface successfully.

BR,

Viet

Yes, we have got 2x2x16 bit controllers to work with DM8148.

We used the guide in the TRM and the DDR3-sheet of our DDR3 device, Timings have been measured by the tool above.
We first used a simple program to do some memory tests before going to uboot and configured the DDR3 via the .gel files (i.e. adapted it to our register configurations),
The only discrepancy we encountered that our ddr3 device manufacturer understands something different under page size than the TRM(= just col bits).

(DDR3 1600 used as DDR3 800@400 Mhz).
We left TILER/PAT the same and just modified the LISA and DDR3 specific registers as suggested in the Guide.

hi, all

      we  use 2x16bits ddr2 on DM8148 .we have also measured the timing by the above tool,the difference is that we didn't use DDR1.when we download the u-boot.mini.uart ,the DDR PLL is configured to 400MHZ,but the TeraTerm has no any prints,it seems that the DM8148 is halt !

     can anyone tell me why my dm8148 doesn't work? 

     Is it caused by our disabling of DDR1 ?

    thanks

hi, all

      we  use 2x16bits ddr2 on DM8148 .we have also measured the timing by the above tool,the difference is that we didn't use DDR1.when we download the u-boot.mini.uart ,the DDR PLL is configured to 400MHZ,but the TeraTerm has nothing to prints out,it seems that the DM8148 is halt !

     can anyone tell me why my dm8148 doesn't work? 

     Is it caused by our disabling of DDR1 ?

    thanks

Viet:

From the 8168 forum, I read a TI e2e reply:  You are correct that 4 4Gb x16b devices give a total of 2GB address space, which the device can address.  That is from the HW perspective.  There are still some discussions going on about full support in SW for 4Gb devices.

My specific DM8148 question:

With DM8148, Can I use MT41K256M32 part (contains two 4Gb x 16b) that would allow for 1 device per EMIF and simplify placement and routing?

Patrick

Patrick,

In general, the twin die parts should be OK and function similar to the single die part.  Are you planning to use the MT41K at 1.5V?  It supports 1.35V or 1.5V operation.

Larry

Hi Larry,

There was a post Re: DM8148 DDR3 1.35V where this was mentioned.

I can go either way with my power design if 1.35V is qualified. A bigger question

is in a response from 8168 forum RE: DM8168: DDR3 x16 4Mbit device support

"There are still some discussions going on about full support in SW for 4Gb devices".

Will the DM8148 have software support via PSP for these larger devices?

Thanks for your reply,

Patrick

Quick answers to your questions

#1 . Yes the same .out file will work for all frequencies.  Ideally one should start with low freq first and go upward.

#2   I think this question is related to configuring the EMIF register and not DDR PHY registers. (The SW leveling procedure will help in DDR PHY register tuning).  The EMIF4 register configuration sheet was provided here: http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot

BR,

Viet
 

Jonathan,

I am planning to use DDR3*16 *2 on DDR0 for cost reduction.

Just wanted to know whether the above DDR3 *16 is working fine in your design ?

Thanks

Regards

Sudarshan

Yes it is.

Jonathan,

Could you let me know which DDR3*16 part no. were used ?

Thanks

Regards

Sudarshan

Hello,

I am also facing the similar kind of issue. I am working on a TI8148 board and trying to port U-boot on the production board. Our production board is same as the reference board, only change is we upgraded to 4GB and we have different memory configuration. It was 8x8 banks on the reference board, we upgraded it to 16x8 on our production board. I am trying to do the software leveling based on the reference link http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot . But when I run the DDR3_SlaveRatio_ByteWiseSearch_TI814x.out from CCS, I am getting the ratio values as 0s. 

Can anyone guide me how to resolve this issue?

[CortexA8] Enter 0 for DDR Controller 0 & 1 for DDR Controller 1
0
[CortexA8] DDR START ADDR=0x80000000
[CortexA8]
[CortexA8] Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
0xb3
[CortexA8]
[CortexA8] Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
0x34
[CortexA8]
[CortexA8] Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
0x08
[CortexA8] Enter the input file Name
ti_ddr.txt
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] WR DATA RATIO MAXIMUM VALUE DIDN'T CONVERGE
[CortexA8] WR DATA RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] *********************************************************
[CortexA8] Byte level Slave Ratio Search Program Values
[CortexA8] *********************************************************
[CortexA8] BYTE3 BYTE2 BYTE1 BYTE0
[CortexA8] *********************************************************
[CortexA8] Read DQS MAX 0 0 0 0
[CortexA8] Read DQS MIN 0 0 0 0
[CortexA8] Read DQS OPT 0 0 0 0
[CortexA8] *********************************************************
[CortexA8] Read DQS GATE MAX 0 0 0 0
[CortexA8] Read DQS GATE MIN 0 0 0 0
[CortexA8] Read DQS GATE OPT 0 0 0 0
[CortexA8] *********************************************************
[CortexA8] Write DQS MAX 0 0 0 0
[CortexA8] Write DQS MIN 0 0 0 0
[CortexA8] Write DQS OPT 0 0 0 0
[CortexA8] *********************************************************
[CortexA8] Write DATA MAX 0 0 0 0
[CortexA8] Write DATA MIN 0 0 0 0
[CortexA8] Write DATA OPT 0 0 0 0
[CortexA8] *********************************************************
[CortexA8]
[CortexA8] ===== END OF TEST =====

Dear Jonathan,

Currently I am using DDR3*16 *2 for each DDR EMIF (total four DDR3, 1GMB).

I am also planning to just use DDR3*16 *2 on DDR0 for cost reduction.

Can you tell me

1) Can I just remove two DDR3 in DDR1 EMIC ? Will this work ? What should be care if only use one DDR EMIF ?

2) Do you modify config_512M.bld ? can you share your bld file to me ?

3) How about uboot/kernl ~ which part should be modified ?

thx ~

HB