Hi Champs,
in the SRIO User's Guide SPRUGW1 there's an example on page 70 showing how to program the LSU. It uses the CSL register layer APIs to perform register read and write.
In this example the Full bit is being checked first, then the busy bit is checked. Trying this on the HW it seems that accessing Reg6 to check the Full bit will set the busy bit already. If this behavior is correct the example in the User's Guide is wrong.
Could you please confirm.
Thanks and regards,
one and zero