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C6678 - SRIO programming details of LSU

Hi Champs,

in the SRIO User's Guide SPRUGW1 there's an example on page 70 showing how to program the LSU. It uses the CSL register layer APIs to perform register read and write.

In this example the Full bit is being checked first, then the busy bit is checked. Trying this on the HW it seems that accessing Reg6 to check the Full bit will set the busy bit already. If this behavior is correct the example in the User's Guide is wrong.

Could you please confirm.

Thanks and regards,

one and zero

  • When you do a single read of the LSU reg6, you can determine one of three scenarios:

    1)  Full bit is set, which indicates no more shadow registers.  You have to poll again until full is low to write any registers.

    2)  Full is low, but busy is set.  This means another core has ownership of the registers and is in the process of writing the reg0-5 to cause a transaction.  A core must poll again until it sees bsy low.

    3)  Both Full and BSY are low.  This means which ever core read the reg6 now has the lock on the LSU registers and can write the reg0-5 to cause a transaction.  Any subsequent read of reg6 before reg5 is written, will now return BSY = 1.

     

    So it requires one read of reg6, but you have to look at both fields to determine the next step.  In case #3, one read secures the lock.

     

    Regards,

    Travis

  • Hi Travis,

    thanks for the explanation. If I understand you correctly then the before mentioned example on page 70 in the User's Guide is actually wrong. The code first checks the full bit - then after that the busy bit. At this stage the code would be deadlocked.

    I believe we need to correct the example in the User's Guide ....

    Kind regards,

    one and zero

  • I'll have the user guide example modified to reflect the correct operation.

     

    Regards,

    Travis