Other Parts Discussed in Thread: AM1808, AM1810
Hello,
I'm trying to chase down the valid options for configuring the AM1808's PLL settings.
For my reference I've been using the June 2011 version of the AM1808 data sheet (i.e. SPRS653B) and the May 2011 version of the AM1808/AM1810 Arm Microprocessor System Reference Guide (i.e. SPRUGM9B).
I've run into either conflicting specifications, or a misunderstanding on my part, that I'd appreciate some help in clearing up:
Table 5.4 in the data sheet lists PLLOUT as being limited between 300 MHz and 600 MHz.
Section 6.2, and table 6.3, of the system reference guide specifies that "Div1 mode" is not supported, and specifically that POSTDIV must be greater or equal to 1.
Am I correct in my understanding that if both of those specifications are true, then the maximum CPU speed would be 300 MHz?
My understanding is that the 600 MHz limit to PLLOUT applies to the point in between the "PLL" and the "POSTDIV" blocks in figure 5.9 of the data sheet, and that a minimum of division by 2 (when using a POSTDIV of 1) would limit everything downstream to a maximum of 300 MHz, in contradiction to the AM1808's advertised speed grade.
Is the acceptable internal range of the PLL actually greater than 600 MHz? Is "Div1 mode" (a POSTDIV of 0) actually supported? Or am I simply incorrect in my understanding?
Thank you,
--trock
ps. If the minimum legal value of POSTDIV really is 1, then I'd encourage TI to update the POSTDIV register description in section 7.3.23 of the reference guide accordingly.
