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TMS320C6747 PLL ISSUE

Other Parts Discussed in Thread: TMS320C6747

We are  using custom made tms320C6747 board with 24Mhz crystal and configured CPU frequency to 300MHz

i.e. CPU Frequency =  24 (Crystal)* 25(PLL MULT) /2(POSTDIV).

we are  making use of OBSCLK output pin with OSCDIV (Divide ratio = 10)  to verify the crystal oscillator clock  ,

CPU clock and all peripheral clocks (SYSCLK1 to SYSCLK7).

For SYSCLK1 ,SYSCLK2,SYSCLK4  we are   maintaining the fixed clock ratios  1 , 2 , 4  respectively.

Crystal oscillator clock ( 24Mhz) ,SYSCLK1 and SYSCLK7 showing the frequency as desired.

Rest of the system clocks  show different frequencies.

Example :a) SYSCLK2 is configured with default divide ratio of 2 and Divide ratio of 10(OSCDIV ) (300MHz /2)/10 = 15MHz/),
                       but it shows 30Mhz at OBSCLK ..

                  b) SYSCLK4 is configured with default divide ratio of 4 and Divide ratio of 10(OSCDIV ) (300MHz/4)/10  = 7.5MHz) ,
                        but it shows  15Mhz at OBSCLK

i am using c6747 gel file which is provided by ti.

 

Regards

Ravi prasad B S