Erroneous USB0 RXCOUNT during bulk OUT transfer

Gonzalo

Did you see this issue with DMA mode enabled?

If so can you try with PIO mode, whether the issue is seen.

Regards

Ravi B

Hello Ravi,

DMA is disabled.

Best regards,

Gonzalo

Gonzalo

This is strange behavior. what is RX and TX endpoint number used?  Can you try with different endpoint numbers (not sharing same tx and rx).  Are you using linux or non-linux?

Regards

Ravi B

Yes, it is strange.

Endpoints are not sharing Rx & Tx, I'm not using Linux.

Endpoint 1: Interrupt IN
Endpoint 2: Bulk IN
Endpoint 3: Bulk OUT

Regards,
Gonzalo

Also...

I had also tried swapping the endpoints for Bulk IN & OUT and had the same result: IN (Tx) works OK but OUT transfers are not being read correctly.

By the way, there is no register to explicitly configure an endpoint for IN or OUT, right? I assume this is achieved through the Tx&Rx FIFO size and address configurations... or should I be setting the TX FIFO registers to something instead of leaving them with default values and just configuring the RX FIFO registers for the OUT endpoint.

Regards,
Gonzalo

Anyone from TI with any suggestion?

I tried posting my problem in the Sitara forum (given the fact that it has the same USB controller as the OMAPL-1x) but the "forum moderation team" erased my post so I assume TI don't expect a Sitara user could have an answer for me.

Thanks in advance...
Gonzalo

Ganzalo

I suspect there may be problem in configuring FIFO space for RX- endpoints. Can you recheck the FIFO space for endpoints are configured properly.

Regards

Ravi B

Yes, I suspect there might be. That's why I was asking questions about their configuration:

"By the way, there is no register to explicitly configure an endpoint for IN or OUT, right? I assume this is achieved through the Tx&Rx FIFO size and address configurations... or should I be setting the TX FIFO registers to something instead of leaving them with default values and just configuring the RX FIFO registers for the OUT endpoint."

Q1 = So, what should I do with the TX FIFO if I only need a given endpoint for RX (bulk OUT transactions)?

Q2 = What is it that at the end determines an endpoint to be configured as IN or OUT?

Thank you,
Gonzalo

Ganzalo

For endpoint 0, for TX/RX (IN or OUT) the fifo address space is same. Only for endpoint-1 to 15 you need to configure the saperate FIFO space.

The FIFO configuration registers available from offset (0X62 to 66). You need to specific endpoint number to which FIFO configuration is done. This can be done thought INDEX register. (offset 0x0E)

Regards

Ravi B

Hello Ravi,

Thanks for your reply, but I'm afraid that still doesn't answer my problem.

Please read my following comments carefully, as it's 3:30AM for me and the only reason I'm awake is so that I can hopefully have a quick response from you and be able to reply back in case I need further support.

I am aware of what you said in your previous post, the only thing that doesn't match with what I've seen in the USB controller document (SPRUFM9H, July 2010) is the fact that you're mentioning endpoints 1 to 15 and as far as I know this controller only has endpoints 1 to 4.
Question = Was the 15 a typo and you really meant 4 or what am I missing? Should I be looking at another document for the OMAPL-138 USB controller?

I suspect the configuration problem is only for the particular case of an endpoint configured for Bulk OUT transfers since, as I've said before, the enumeration is done OK, meaning that Tx and Rx are working OK with Endpoint 0. Also, I have configured an endpoint for Bulk IN transfers and that is also working OK too so is not like the software is totally lost.

This is what I'm doing to configure, say endpoint 1 for Bulk OUT transfers (Max packet size = 64):

1. INDEX = 1 (access endpoint 1 registers)
2. RXFIFOSZ = 3 (set fifo size to 64 bytes)
3. RXFIFOADDR = 8 (start after 64 bytes of EP0... 8 x 8 = 64)
4. TXFIFOSZ = 3 (set fifo size to 64 bytes)
5. TXFIFOADDR = 16 (start after 128 bytes of EP0 + EP1RX... 8 x 16 = 128)
6. RXMAXP = 64 (maximum packet size for receive = 64 bytes)
7. TXMAXP = 64 (maximum packet size for transmit = 64 bytes)
8. PERI_RXCSR.ISO = 0 (clear ISO bit to enable the receive endpoint for Bulk transfers)
9. PERI_TXCSR.MODE = 0 (clear MODE bit to enable it as Rx)
10. If PERI_RXCSR bits RXPKTRDY or FIFOFULL are set, then set PERI_RXCSR.FLUSHFIFO to 1 to flush the fifo and clear RXPKTRDY too.
11. PERI_RXCSR.CLRDATATOG = 1 (reset endpoint data toggle to 0)

Question = Do you see anything wrong in the sequence above? Should I change anything?

Note, I was originally leaving the TX FIFO registers untouched for the endpoint being configured for RX (OUT transfers) and I asked whether that was OK or not so at the end I ended up configuring it anyway but nothing changed.

I do pretty much the same sequence for Bulk IN transfers except that I clear PERI_TXCSR.ISO bit to enable TX endpoint for Bulk and set PERI_TXCSR.MODE to 1 to enable the endpoint direction as Tx. So far I don't have any problem with TX.

I truly appreciate the time you can take to read this and analyze in detail.

Best regards,

Gonzalo

Gonzalo, Good to see it is working.

I did not understood what is the fix did in WinCE USB driver. Do you mean FIFO regsiters are read as part of debug dump?

Regards

Ravi B