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Original question:

AM6442: Throughput benchmark to R5F <--> DRAM

AM6442: Benchmark details

Chris
Intellectual 301 points

Part Number: AM6442

Dear TI team,

I have been referring the benchmark application note. I have noted the R5F latencies are mentioned in nanoseconds. Does that mean, "to read One Byte of data from External DDR, the R5F core would face a latency of 280ns " ? Is it possible to mention the same in terms of MB/s? 

Thank you

Chris

  • 0
    TI__Mastermind 27050 points

    Chris,

    The memory latency numbers cannot be directly translated to bandwidth. Usually, the latency benchmark is the most critical metric for realtime applications. The benchmark app report does include memory latency and bandwidth achievable for the Cortex A53 cores (let_mem_rd for latency, bw_mem for bandwidth).

    If you create a benchmark, typically the R5 core will have a single cache line (32bytes) in flight per the latency listed for simple SW based memory read or copy loops. For writes there can be multiple lines in flight. For higher bandwidth you would use the block copy DMA (BCDMA) to page in and out data to the TCM memory.

      Pekka

  • 0 in reply to Pekka Varis
    Intellectual 301 points

    Thanks Pekka,

    In our application, from R5F core we need to transfer data to a shared location in DDR at a rate of 1MB/s and all other cores has to access shared location in every 1 ms. Basically we are estimating the time consumption by each cores while accessing the shared memory locations. So can we assume the latencies are marked to read 32 bytes of data from the respective memory locations?

    Thank you

    Chris

  • +1 in reply to Chris
    TI__Mastermind 27050 points

    Yes for a very rough estimate one cache line per latency is good. Overall 1MB/s is a low bandwidth load, the ballpark on R5 max bandwidth writing to DDR4/LPDDR4 will be at least an order of magnitude higher probably closer to two orders of magnitude higher.

    One access per millisecond from other cores is even lower. Assuming this is a small access (cache line) even the jitter from the interference will be smaller than for example the DDR refresh caused jitter.

      Pekka