OMAP-L13X USB 2.0

Frank

Other Parts Discussed in Thread: OMAP-L138

Hello,

I've some questions related to the USB2.0 documentation (sprufm9h.pdf).
I'm using a LOGIC PD L138 eXperimenter board with the following versions
on the ARM side of the OMAP-L138:
- CCS Version 4.2.1.00004
- SYS/BIOS 6.30.03.46

Implemented is a virtual COM port on my Laptop (Windows XP Professional, SP3).
The two bmAttributes for the endpoint descriptors (EP1 IN and EP1 OUT) within the configuration descriptor are set to "Bulk".

FLUSHFIFO questions:
====================
sprufm9h.pdf describes on page 32/165 resp. on page 34/165 the Setup for Bulk In/Out Transactions.
In chapter 2.7.1.2.1.1 Setup the following statement is made:
"When the endpoint is first configured (following a SET_CONFIGURATION or SET_INTERFACE command on Endpoint 0), the lower byte of PERI_TXCSR should be written to set the CLRDATATOG bit (bit 6). This will ensure that the data toggle (which is handled automatically by the controller) starts in the correct state.
Also if there are any data packets in the FIFO, indicated by the FIFONOTEMPTY bit (bit 1 of PERI_TXCSR) being set, they should be flushed by setting the FLUSHFIFO bit (bit 3 of PERI_TXCSR)."

Similar statement can be found for the Bulk Out Transactions (see chapter 2.7.1.2.2.1)

However, the description for the FLUSHFIFO in chapter 4.35 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) on page 126/165 has the following note:
"Note: FlushFIFO has no effect unless the TXPKTRDY bit is set. Also note that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO."

Q1: When receiveing on EP0 a SET_CONFIGURATION do I need to set the TXPKTRDY in addition to the FLUSHFIFO bit (when FIFONOTEMPTY bit is set)?

Q2: If the FIFO is double-buffered, do I need to check the FIFONONEMPTY a second time before setting the FLUSHFIFO bit or can I set the bit just twice?

Next question is similar to Q2, just for the receive side.
Q3: If the FIFO is double-buffered, do I need to check the RXPKTRDY a second time before setting the FLUSHFIFO bit or can I set the bit just twice?

EMUR questions:
===============
sprufm9h.pdf describes on page 101/165 the Emulation Register (EMUR).
Q4: Where can I find a detailed description of the 3 bits resp. how do I need to set these register when using an emulator?
Q5: What is the "CBA 3.0 emulation interface"?

Thanks,
Frank

over 14 years ago

0 Gonzalo Victorio over 14 years ago

Prodigy 130 points

Hello Frank,

I'm afraid I don't have answers for you but I reckon you're doing something similar to what I'm trying to do: USB as a COM port, Bulk IN and OUT transactions.

I already have the enumeration and TX (IN transactions) going on, but I'm having problems with the OUT transactions... the controller says in RXCOUNT that I have received ~8K of data when in reality only 1 character was sent.

Q = Have you managed to get Bulk OUT transactions working on the OMAPL-138?

Regards,
Gonzalo

0 Frank over 14 years ago in reply to Gonzalo Victorio

Intellectual 985 points

Hello,

anybody from the TI experts there, who can answer my questions?

Gonzalo,
to your Q: a few days ago, I could transmit some data from PC to OMAP.
Highly appreciate if you could open a separate ticket for your problems!

Thanks,
Frank

0 Frank over 14 years ago in reply to Frank

Intellectual 985 points

Hello,

anybody from the TI experts there?

Frank

0 Kiung Chung Wong over 14 years ago

Expert 2110 points

Hi Frank,

Just share with you the function that is called when SET_CONFIGURATION request is received in my driver.

Q1: No need to set TXPKTRDY because no data is sent to host for SET_CONFIGURATION request.

Q2 & Q3: I did not use double-buffered, so I am not quite sure. But, from the code, I think you just need to write the RXCSR/TXCSR twice with the same value.

STATUS USBDrv_ConfigureEndpoint(USBDRV_ENDPOINT endpoint, UINT8 direction,
UINT8 transferType, UINT16 packetSize, BOOL dmaEnable)

{

UINT16 csr = 0;

switch (direction)
{
case USB_DIR_OUT:
REG_WRITE(ENDPOINT_STS_CTL_REGs[endpoint]->RXMAXP, packetSize);

  {
   if (transferType == USBPIPE_ISOCH)
   {
    csr |= RXCSR_P_ISO;
   }
   else if (transferType == USBPIPE_INT)
   {
    /* Disable the transmission of NYET handshakes in high-speed mode */
    csr |= RXCSR_P_DISNYET;
   }

   if (is_dma_capable() && (dmaEnable == TRUE))
   {
    csr |= RXCSR_P_DMAEN;
   }

/* Ensure the data toggle starts in the correct state */
csr |= RXCSR_P_CLRDATATOG;

   /* If there are any data packets in the FIFO, they should be flushed. */
   if (REG_TEST_BIT(ENDPOINT_STS_CTL_REGs[endpoint]->RXCSR, RXCSR_P_RXPKTRDY))
   {
    csr |= RXCSR_P_FLUSHFIFO;
   }
  }

REG_WRITE(ENDPOINT_STS_CTL_REGs[endpoint]->RXCSR, csr);

#if 0 /* NOTE: It may be necessary to set this bit twice in succession if double buffering is enabled. */
REG_WRITE(ENDPOINT_STS_CTL_REGs[endpoint]->RXCSR, csr);
#endif

break;

case USB_DIR_IN:
REG_WRITE(ENDPOINT_STS_CTL_REGs[endpoint]->TXMAXP, packetSize);

  {
   if (transferType == USBPIPE_ISOCH)
   {
    csr |= TXCSR_P_ISO;
   }
   else if (transferType == USBPIPE_INT)
   {
    /* Enable the continuous toggle of the data toggle bit ? */
    /*csr |= TXCSR_P_FRCDATATOG;*/
   }

csr |= TXCSR_P_MODE;

   if (is_dma_capable() && (dmaEnable == TRUE))
   {
    csr |= (TXCSR_P_DMAEN | TXCSR_P_DMAMODE);
   }

/* Ensure the data toggle starts in the correct state */
csr |= TXCSR_P_CLRDATATOG;

   /* If there are any data packets in the FIFO, they should be flushed. */
   if (REG_TEST_BIT(ENDPOINT_STS_CTL_REGs[endpoint]->TXCSR, TXCSR_P_FIFONOTEMPTY))
   {
    csr |= TXCSR_P_FLUSHFIFO;
   }
  }

REG_WRITE(ENDPOINT_STS_CTL_REGs[endpoint]->TXCSR, csr);

#if 0 /* NOTE: It may be necessary to set this bit twice in succession if double buffering is enabled. */
REG_WRITE(ENDPOINT_STS_CTL_REGs[endpoint]->TXCSR, csr);
#endif

break;

default:
assert(0);
}

return (OK);

}

rgds,

kc Wong

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OMAP-L13X USB 2.0