TDA4VM: A question about C7x cache

Part Number: TDA4VM

Hi, experts

I am currently working on a task whose main purpose is to add a memory area on the DDR for use by C66 and C7x.

I know that we can use the cache invalidation function to avoid cache consistency issues.

But we use this memory frequently, I think calling this function frequently may be time-consuming.

So, I plan to set this memory to non cached to avoid this problem.

For C66, I found a way to set non cache in the $(RTOS_SDK)/vision_apps/platform/j721e/rtos/c66x_x/main.c

void appCacheMarInit(void)
{
#ifdef SYSBIOS
    /* enable cache for cached sections */
    Cache_setMar((Ptr)DDR_C66x_1_DTS_ADDR, DDR_C66x_1_DTS_SIZE, Cache_Mar_ENABLE);
    Cache_setMar((Ptr)DDR_C66X_1_LOCAL_HEAP_ADDR, DDR_C66X_1_LOCAL_HEAP_SIZE, Cache_Mar_ENABLE);
    Cache_setMar((Ptr)DDR_C66X_1_SCRATCH_ADDR, DDR_C66X_1_SCRATCH_SIZE, Cache_Mar_ENABLE);
    Cache_setMar((Ptr)DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_SIZE, Cache_Mar_ENABLE);

    /* disable cache for non-cached sections */
    Cache_setMar((Ptr)DDR_C66x_1_IPC_ADDR, DDR_C66x_1_IPC_SIZE, Cache_Mar_DISABLE);
    Cache_setMar((Ptr)APP_LOG_MEM_ADDR, APP_LOG_MEM_SIZE, Cache_Mar_DISABLE);
    Cache_setMar((Ptr)TIOVX_OBJ_DESC_MEM_ADDR, TIOVX_OBJ_DESC_MEM_SIZE, Cache_Mar_DISABLE);
    Cache_setMar((Ptr)IPC_VRING_MEM_ADDR, IPC_VRING_MEM_SIZE, Cache_Mar_DISABLE);
    Cache_setMar((Ptr)TIOVX_LOG_RT_MEM_ADDR, TIOVX_LOG_RT_MEM_SIZE, Cache_Mar_DISABLE);
#else
    /* enable cache for cached sections */
    CacheP_setMar((void *)DDR_C66x_1_DTS_ADDR, DDR_C66x_1_DTS_SIZE, CacheP_Mar_ENABLE);
    CacheP_setMar((void *)DDR_C66X_1_LOCAL_HEAP_ADDR, DDR_C66X_1_LOCAL_HEAP_SIZE, CacheP_Mar_ENABLE);
    CacheP_setMar((void *)DDR_C66X_1_SCRATCH_ADDR, DDR_C66X_1_SCRATCH_SIZE, CacheP_Mar_ENABLE);
    CacheP_setMar((void *)DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_SIZE, CacheP_Mar_ENABLE);

    /* disable cache for non-cached sections */
    CacheP_setMar((void *)DDR_C66x_1_IPC_ADDR, DDR_C66x_1_IPC_SIZE, CacheP_Mar_DISABLE);
    CacheP_setMar((void *)APP_LOG_MEM_ADDR, APP_LOG_MEM_SIZE, CacheP_Mar_DISABLE);
    CacheP_setMar((void *)TIOVX_OBJ_DESC_MEM_ADDR, TIOVX_OBJ_DESC_MEM_SIZE, CacheP_Mar_DISABLE);
    CacheP_setMar((void *)IPC_VRING_MEM_ADDR, IPC_VRING_MEM_SIZE, CacheP_Mar_DISABLE);
    CacheP_setMar((void *)TIOVX_LOG_RT_MEM_ADDR, TIOVX_LOG_RT_MEM_SIZE, CacheP_Mar_DISABLE);
#endif
}

For MCU, I found a method to set non cache in the $(RTOS_SDK)/vision_apps/platform/j721e/rtos/mcux_x/j721e_mpu_cfg.c

    {
        /* Region 7 configuration: Ring buffer */
        .regionId         = 7U,
        .enable           = 1U,
        .baseAddr         = IPC_VRING_MEM_ADDR,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_64MB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 1U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)FALSE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
        .memAttr          = 0U,
    },
    {
        /* Region 8 configuration: Ring buffer */
        .regionId         = 8U,
        .enable           = 1U,
        .baseAddr         = DDR_MCU2_0_IPC_ADDR,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 1U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)FALSE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
        .memAttr          = 0U,
    },

But I didn't find the relevant setup method in C7x.

C7x's Mmu_map function does not perform cached or non cached operations on memory regions.

    retVal = Mmu_map(APP_LOG_MEM_ADDR, APP_LOG_MEM_ADDR, APP_LOG_MEM_SIZE, &attrs, is_secure);
    if (retVal == FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(TIOVX_OBJ_DESC_MEM_ADDR, TIOVX_OBJ_DESC_MEM_ADDR, TIOVX_OBJ_DESC_MEM_SIZE, &attrs, is_secure);
    if (retVal == FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(IPC_VRING_MEM_ADDR, IPC_VRING_MEM_ADDR, IPC_VRING_MEM_SIZE, &attrs, is_secure);
    if (retVal == FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(DDR_C7x_1_IPC_ADDR, DDR_C7x_1_IPC_ADDR, DDR_C7x_1_IPC_SIZE, &attrs, is_secure); /* ddr            */
    if (retVal == FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(TIOVX_LOG_RT_MEM_ADDR, TIOVX_LOG_RT_MEM_ADDR, TIOVX_LOG_RT_MEM_SIZE, &attrs, is_secure);
    if (retVal == FALSE)
    {
        goto mmu_exit;
    }

Code is from $(RTOS_SDK)/vision_apps/platform/j721e/rtos/c7x_1/main.c

However, one thing is certain, that is, the IPC_VRING_MEM needs to be set to non cached. I believe C7x has done this.

But how does C7x set a certain memory region to be non cached?

Appendix:

SOC: TDA4VM

Linux: ti-processor-sdk-linux-j7-evm-08_01_00_07

RTOS: ti-processor-sdk-rtos-j721e-evm-08_01_00_11

Best regards,

Tao