IBL from I2C 400Khz

The speed of the interface can be set using the BOOTMODE pins.  Section 3.5 of the C66x DSP BootloaderUsers Guide includes Table 3-17 which describes the different boot settings for the I2C boot.  This bits are associated with the BOOTMODE pins for the DSP and are defined in Table 2-5 of that same document.  To set the speed to 400KHz bit 8 of the I2C Master Mode Device Configuration should be set to 1.  Bit 8 of the I2C Device Configuration equates to BOOTMODE[11].  If you set the switch on the EVM for BOOTMODE[11] to high is should use 400KHz mode for the I2C bootloader.

Hi,

I have the same problem.

The answer is not correct : I don't succeed to change speed to 400 Khz like this.

What is the source code from the IBL process I can change to make this modification

Thanks

GAUTHIER Jean-Michel is right. it doesn't save any time when I set the switch to I2c 400KHz On 6678evm. I can't understand why? How can we save ibl boot time ?

Bill's response is correct.  The BOOTMODE pins set the initial speed of the I2C interface.  This is explained in the KeyStone Bootloader User’s Guide.  Note that the frequency chosen is conservative since it is not certain of the core clock frequency during the initial boot process.  However, there is an additional opportunity to boost the performance of this interface.  The first locations loaded from the memory attached to the I2C port is a boot table.  This is also explained in the KeyStone Bootloader User’s Guide.  This boot table contains entries such that the ROM boot program can program the core PLL and set the I2C clock rate optimally.

The IBL code in the KeyStone EVMs is currently configured for a sub-optimal rate so that it can robustly load even if the core clock input rate is increased.  The settings in this boot table override the settings from the DIP switches.  Customer designs can shorten this time by optimizing these settings.  The IBL program is also larger than most customers need since it contains multiple additional boot loaders like TFTP and NAND boot.  The IBL load time can be shortened by making the IBL code optimized for a particular application.

Tom

Are you still facing this issue? i can think about one more possibility.The map file that is used for the generating the ibl.bin file uses only 200kHz. If that is the case, then the boot table will not be using 400khz. You need to change the map file and recompile the ibl. Please let me know if you see any improvements.

Thanks,

Arun.

There are two problems. One is the EEPROM chipset can't work exceed 100kHz, Is that right? The other one is that I can see the i2c frequency is set in iblInit.c->main->i2cInit. It set at 100Khz frequency. Are there any place I can set the i2C frequency in ibl? I will test torrow. Thanks for all.

The I2C EEPROM on the EVM can support both 100KHz and 400KHz operation according the the specification of the part.  Are you referring the an EEPROM on your board?

The map file that is used for the generating the ibl.bin file uses only 200kHz.  Which map file? where does it locate? Thanks

Hi,

I succeed to have better boot time with the following modifications :

file ibl\src\main\ibliniti2c.c :

BOOT_MODULE_FXN_TABLE *iblInitI2c (void)

{

    ………………..

    hwI2Cinit (IBL_CFG_I2C_DEV_FREQ_MHZ,        /* The CPU frequency during I2C data load */

               DEVICE_I2C_MODULE_DIVISOR,       /* The divide down of CPU that drives the i2c */

               400,                                /* IBL_CFG_I2C_CLK_FREQ_KHZ: I2C data rate used during table load */

               IBL_CFG_I2C_OWN_ADDR);           /* The address used by this device on the i2c bus */

…………

}

 Rq : changing  variable IBL_CFG_I2C_CLK_FREQ_KHZ in file ibl\src\cfg\c66x\iblcfg.h does not work with the compilation make file !!!!   

I also don't understand what is the Boot Parameter table and Map files  !!!!

• I also reduce significantly the boot time by changing EMIF configuration in the file \ibl\src\util\iblConfig\src\device.c

file  ibl\src\hw\emif25\emif25.c  :

Int32 hwEmif25Init (int32 cs, int32 busWidth, bool wait, bool nand)

{

…..

    reg = EMIF25_SET_ASYNC_WAIT(reg, v);

 /*     bits R_HOLD : Number of EMIF16 clock cycles for which EMIFA[23:0], EMIFBE[1:0] and CE are held valid after

    EMIFOE has been deasserted, minus one cycle. The reset value is 8 cycles. */

       reg &= 0xffffff8f;   /* RAZ des bits R_HOLD */

       reg |= 0x00000060;   /*  6 cycles */

/*     bits R_STROBE : Number of EMIF16 clock cycles for which EMIFOE is held active, minus one cycle. The reset value is

64 cycles. This field cannot be zero when EW = 1.*/  

       reg &= 0xffffe07f;   /* RAZ des bits R_STROBE */

       reg |= 0x00000780;   /* 16 cycles */

/*     Number of EMIF16 clock cycles from EMIFA[23:0], EMIFBE[1:0] and CE being set to EMIFOE asserted,

minus one cycle. The reset value is 16 cycles.*/

       reg &= 0xfffe1fff;   /* RAZ des bits R_SETUP */

       reg |= 0x0000c000;   /*  6 cycles */

    DEVICE_REG32_W (DEVICE_EMIF25_BASE + EMIF25_ASYNC_CFG_REG(cs-2), reg);

…..

}

Values are to be adjusted according to NAND datasheets ...

Jean-Michel

The MAP file i am talking is i2crom.map in the the C:\mcsdk2_05\mcsdk_2_00_05_17\tools\boot_loader\ibl\src\make\ibl_c66x

You can change this to accelerate. What ever setting you make in the boot parameter table before running the IBL, will be overwritten by the parameter setting that is done in the first block of the css file loaded in the i2c 0x51. Try this change and see if this helps accelerate the transfer.

Thanks,

Arun. 

GAUTHIER Jean-Michel is right. I change the IBL_CFG_I2C_CLK_FREQ_KHZ in  ibl\src\cfg\c66x\iblcfg.h file. You can make clean first. It can save boot time greatly. I will change the map file later. Thanks for all!