Hello TI experts:
We have a video pipeline required by our customer :
1. 4 x [ Ti953 1.5M YUV422/UYVY camera ] connected to Ti9702 deserializer
2. Ti9702 deserializer integrate four camera streams in a interleaved way
3. Ti9702 send interleaved frames , TDA4VM receive frames with csirx driver
4. TDA4VM puts interleaved frames in memory buffers
5. TDA4VM csitx driver send interleaved frames to max96717. while customer requires 4 interleaved frames should carry 4 virtual channels So they can process it correctly.
Four customer's special requirement, we can not adjust Ti9702 to basic sync mode.
So my questions are:
1. Is the four interleaved frames put in RAM(in above step 4) still carry virtual channels information? Or TDA4VM csirx driver has processed and removed the information in csi header packet?
2. Let's say the four interleaved frames only contain pixel data, Is it possible for csitx driver to add virtual channel information on the four interleaved frames(every line?)?
