Other Parts Discussed in Thread: AM625
Hi,
I apologize in advance but I've only done a quick 30 minute review of the AM623x Datasheet and TRFM. I would like to interface the GPMC to a CPLD and FPGA. The issue is I want to clock the GPMC bus @ 43.75 MHz. It appears that GPMC_FCLK is limited to 100 MHz or 133 MHz. Is there a way to set GPMC_FCLK to 43.75 MHz?
Regards,
Davey