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AM625: Supported DDR4 SDRAM Combinations

Daisuke Maeda
Guru 20095 points
Part Number: AM625

In the "AM62x DDR Board Design and Layout Guidelines", DDR4 SDRAM combinations for AM62x allow 1 x 16-bit or 2 x 8-bit device configurations.

AM62x DDR Board Design and Layout Guidelines
www.ti.com/.../sprad06.pdf

Can a device configuration with more SDRAMs, e.g., 2 x 16-bit, be used?

Is DDR0_CS1_n not supported?

Best regards,

Daisuke

  • +1
    TI__Guru* 78810 points

    Daisuke, the AM62x DDR Layout Guidelines appnote is in the process of getting updated.  We do support dual rank DDR4 designs, however any design with multiple loads on the address bus must use VTT termination.  We also only support point to point connections for the data bus, so 2 x16 devices could not be used since AM62x only supports one x16 channel.

    Regards,

    James

      

  • 0 in reply to JJD
    Guru 20095 points

    Hi James-san,

    Thank you for your reply.

    I think DDR0_CS1_n should be clearly marked as not supported or "Reserved".

    Best regards,

    Daisuke

  • 0 in reply to JJD
    Guru 20095 points

    Hi James-san,

    I have an additional question.

    How many Gbytes are supported for DDR4?

    In "1 Features" on the datasheet, the maximum address range is 8 Gbytes for DDR4.

    – Max addressable range
    • 8GBytes with DDR4
    • 4GBytes with LPDDR4

    The 17 pins (DDR0_A[13:0], DDR0_RAS_n, DDR0_CAS_n, DDR0_WE_n) for Row addressing should support up to 2 Gbytes, no?

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Guru* 78810 points

    Daisuke, AM62x does support dual rank, so CS1n is supported. 

    There are 17row, 10column,and 4 bank bits to give 4GByte, and then dual rank will be 8GBytes

    Regards,

    James

  • 0 in reply to JJD
    Guru 20095 points

    Hi James-san,

    Thank you for your reply.

    Any references for the dual rank configuration?

    Has the dual rank configuration been tested by TI?

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Guru* 78810 points

    Yes, we have tested a dual rank LPDDR4 design.  We expect dual rank DDR4 to also work, but have not specifically tested that configuration.

    Regards,

    James

  • 0 in reply to JJD
    TI__Guru* 78810 points

    Just to add to this, we could potentially support a dual rank DDR4 design with something like a  MT40A4G8, in a 2 x8 configuration.  As stated earlier, this would require VTT termination for addr/ctrl signals.  It is highly encouraged to perform signal integrity simulations for your board.

    Regards,

    James

  • 0 in reply to JJD
    Guru 20095 points

    Hi James-san,

    Thank you for your reply.

    I understand that AM62x can potentially support a dual die package such as the MT40A4G8, but can NOT support 2 x single die packages for a dual rank configuration since the data bus only supports point-to-point connection, is that correct?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Guru* 78810 points

    Daisuke, this is correct.

    Regards,

    James

  • 0 in reply to JJD
    Guru 20095 points

    Hi James-san,

    Thank you for your reply.

    I would like to confirm one more point.

    The MT40A4G8 has 8 data buses, so it is potentially possible to use 2 x MT40A4G8s for a dual-rank configuration with 16-bit connections, is that correct?

    Best regards,

    Daisuke

  • 0 in reply to JJD
    Guru 20095 points

    Hi James-san,

    Daisuke Maeda said:
    The MT40A4G8 has 8 data buses, so it is potentially possible to use 2 x MT40A4G8s for a dual-rank configuration with 16-bit connections, is that correct?

    An MT40A4G8 is 4 Gbytes (32 Gbits), so 2 x MT40A4G8s will be needed for 8 Gbytes.

    Is it not supported to use 2 x MT40A4G8s for a dual-rank configuration with 16-bit connections?

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Guru* 78810 points

    Daisuke, 2x MT40A4G8 can be supported.  Each device would be connected to each data byte.  The address/ctrl signals would be connected in fly-by topology with VTT termination.    I would recommend performing board level simulations to ensure proper signal integrity.  

    Regards,

    James

  • 0 in reply to JJD
    Guru 20095 points

    Hi James-san,

    Thank you for your reply.

    I would like to suggest to our customer to design a configuration using 2x MT40A4G8s.

    In Micron, the following part numbers seem to be applicable.

    www.micron.com/.../mt40a4g8baf-062e
    www.micron.com/.../mt40a4g8nea-062e

    Best regards,

    Daisuke