Rank

It's true that a group of individual memory devices collectively connected to provide the full data bus is referred to as a rank.  If a memory architecture has a 64bit data bus and has four x16bit DDR3 components it has a single rank.  If the memory architecture has two ranks it would have eight x16bit components with two connections for each of the data bits.  In this architecture there is still a single set of address and command lines connected in fly-by to each of the eight memories but there is a group of pins referred to as the control group that are unique to each rank.  These pins are DDRCEx, DDRCKEx and DDRODTx.  In addition the C66x components provides two sets of clock lines which are also unique to each rank, DDRCLKOUTPx/Nx.  If a single rank system is used DDRCE0, DDRCKE0, DDRODT0 and DDRCLKOUTP0/n0 are connected in a fly-by manner to each of the DDR3 memory components and DDRCE1, DDRCKE1, DDRODT1 and DDRCLKOUTP1/N1 are left unconnected.  In a dual rank memory architecture these pins are connected to the second rank of DDR3 memory components.

The dual-rank memory architecture adds a high degree of complexity to the routing of a PCB due to the dual connections to the data lines.  If possible single rank DDR3 memory architectures are recommended.  A good reference for the connection and routing of dual rank memory architectures can be found in the JEDEC Standard No. 21C Page 2.20.19-1 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Unbuffered DIMM Design Specification.