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PROCESSOR-SDK-AM335X: adding GPIO pin interrupts

Part Number: PROCESSOR-SDK-AM335X
Other Parts Discussed in Thread: AM3351

AM3351 Custom Board
SDK 8.02

I am trying to define GPIO interrupts in my DTS but they are not configured after boot. I first define the pin(s) in the pinmux_gpio_pins node, and then define the GPIO in the &gpio2 node with the interrupt_parent and interrupts as seen below.

&am33xx_pinmux {
	pinctrl-names = "default";
    pinctrl-0 = <&gpio_pins>;

    gpio_pins: pinmux_gpio_pins {
		pinctrl-single,pins = <
		    /* gpiochip1: GPIOs 32-63  */
            AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE7)	    /* nPFO (V18) gpmc_be1n.gpio1[28]) */
        >;
    };
};

&gpio1 {
	nPFO {
		gpio-hog;
		gpios = <28 GPIO_ACTIVE_LOW>;
		input;
		interrupt-parent = <&gpio1>;
		interrupts = <60 IRQ_TYPE_LEVEL_LOW>;
	};
};

After boot, I `cat /proc/interrupts` but do not see my interrupt.

# cat /proc/interrupts
           CPU0
 16:      98945      INTC  68 Level     clockevent
 17:          0      INTC   3 Level     arm-pmu
 19:          0      INTC  96 Level     44e07000.gpio
 20:        404      INTC  72 Level     44e09000.serial
 21:         96      INTC  70 Level     44e0b000.i2c
 28:          0      INTC  65 Level     48030000.spi
 34:          0      INTC  98 Level     4804c000.gpio
 35:      14443      INTC  64 Level     mmc0
 37:          0      INTC 125 Level     481a0000.spi
 38:          0      INTC  32 Level     481ac000.gpio
 39:          0      INTC  62 Level     481ae000.gpio
 40:          0      INTC 111 Level     48310000.rng
 42:        261      INTC  41 Level     4a100000.switch
 43:        126      INTC  42 Level     4a100000.switch
 44:         32      INTC  43 Level     4a100000.switch
 45:       4807      INTC  12 Level     49000000.dma_ccint
 47:          4      INTC  14 Level     49000000.dma_ccerrint
 53:          0      INTC  17 Level     47400000.dma-controller
 56:          0      INTC   0 Level     tps65218
Err:          0

I expect to see something like 

60: 0 4804c000.gpio 28 Edge nPFO

What additional steps are required to configure this interrupt on the GPIO pin?

  • Solved: I needed to get the irq for gpio(60), and then request_irq()

    	irq = gpio_to_irq(60);
    	if (request_irq(irq, pfo_isr, IRQF_TRIGGER_FALLING, "nPFO", pfo_isr)) { /*failed*/ }
    	
    	// where pfo_isr() is the ISR
    	static irqreturn_t pfo_isr(int irq, void *dev_id)

    And now I see my interrupt:

    # cat /proc/interrupts
               CPU0
     16:      41031      INTC  68 Level     clockevent
     17:          0      INTC   3 Level     arm-pmu
     19:          0      INTC  96 Level     44e07000.gpio
     20:        409      INTC  72 Level     44e09000.serial
     21:         96      INTC  70 Level     44e0b000.i2c
     28:          0      INTC  65 Level     48030000.spi
     34:          0      INTC  98 Level     4804c000.gpio
     35:      14395      INTC  64 Level     mmc0
     37:          0      INTC 125 Level     481a0000.spi
     38:          0      INTC  32 Level     481ac000.gpio
     39:          0      INTC  62 Level     481ae000.gpio
     40:          0      INTC 111 Level     48310000.rng
     42:        136      INTC  41 Level     4a100000.switch
     43:        120      INTC  42 Level     4a100000.switch
     44:         16      INTC  43 Level     4a100000.switch
     45:       4806      INTC  12 Level     49000000.dma_ccint
     47:         11      INTC  14 Level     49000000.dma_ccerrint
     53:          0      INTC  17 Level     47400000.dma-controller
     56:          0      INTC   0 Level     tps65218
     57:          0  4804c000.gpio  28 Edge      nPFO Detect