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EMIFA Timing Calculation for OMAP-l138

1258021
Genius 5120 points
Other Parts Discussed in Thread: TMS320DM6446, TL16C754C

Hi,

Thank You for reading.

We have interfaced one of the TI's external UART controller via EMIFA interface.

For this I need to calculate the timing parameters for Programming CSxCFG register.

Do I need to refer the document which is mentioned in the following URL http://processors.wiki.ti.com/index.php/Programming_Asynchronous_EMIF_on_OMAP-L13x_/_C674x_/_AM1x?

Also do I have to refer TMS320DM6446 EMIFA manual on how to calculate the timing parameter values instead of the SPRUFL6E_2010_APR pdf?

Please confirm.

Regards,

GSR

  • 0
    TI__Mastermind 29061 points

    For programming the EMIF for Flash access you would refer to the DM6446 EMIFA manual as the note on the wiki suggests.  However, since you are using a UART controller instead of a Flash device, these formulas will probably not be much help to you.  You'll need to do your own analysis of the UART controller timing requirements and program the EMIF accordingly.  

  • 0 in reply to Gus Martinez
    Genius 5120 points

    Hi Gus Martinez,

    Thank You for the reply.

    I have calculated the timing parameters based on the attached PDF.

    Tcyc=100MHz 10            
                   
      EMIFA ExternalUART Value in nS Calculated Values Divide by Tcyc Considering TA in HOLD
    W_HOLD and R_HOLD are subtracted from TA    		 With 10nS Margin
      W_SETUP t6s 20 20 1 1 2
      W_STROBE t13w 25 25 2 2 3
      W_HOLD MAX(t6h, t16h) + t15d MAX(15, 35) + 85 120 11 8 9
      R_SETUP t6s 20 20 1 1 2
      R_STROBE t7w 85 85 8 8 9
      R_HOLD MAX(t6h, t12h) + t9d MAX(15, 35) + 85 120 11 8 9
      TA 3 3 3 3 3 3

    I have included the Read and Write Cycle delays in R_HOLD and W_HOLD respectively.

    Is it valid considering the Read and Write delays in HOLD timing parameters.

    Also I have considered the Data hold time and Address hold time as maximum of those values. Let me know if that is not correct.

    But, looks the values that I have calculated are crossing the maximum value for W_HOLD and R_HOLD in CSCFG register.

    Is there any other way to include more delay between two successive writes?

    Thank You & Regards,

    GSR 

  • 0 in reply to 1258021
    TI__Mastermind 29061 points

    I'm not sure which UART device you are using, but one thing you can do is increase the SETUP or STROBE timing parameter.  There should be no maximum requirement from the UART device and that would effectively control your cycle to cycle access time (cycle time = SETUP + STROBE + HOLD).  

  • 0 in reply to Gus Martinez
    Genius 5120 points

    Hi Gus Martinez,

    Thank You for replying.

    We are using TL16C754C from TI.

    As of now we don't have the hardware ready...I will post here the results of testing once the Hardware is available.

    Thank You & Regards,

    GSR