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6678 Packet Accelerator Subsystem Clock Speed

Brad Griffis
Guru*** 125430 points

I don't see any requirements related to the clock speed of the packet accelerator subsystem.  For example, what's the max input clock speed to this subsystem?  (Please be clear on whether you are giving the clock speed before or after the hard-wired /2 coming out of the PASS PLL.)  I expected to see requirements for the PLL itself too, i.e. min/max input clock frequency, min/max PLLOUT, etc.

  • 0
    Expert 1120 points

    Hi, Brad

    There is a figure in SPRABI2 page 14 which illustrates the reference range for the clock input of keystone devices:

    And in SPRS691 page 230 has this digram:

     

    At last, in SPRUGZ6 page 16 says: 'The network coprocessor (NETCP) has three primary clock domains:
    1.Packet Accelerator (PA)
    2.Security Accelerator (SA)
    3.Gigabit Ethernet (GbE) Switch subsystem
    Each of these three clock domains share a common source clock, which is expected to operate at 350 MHz. '

    What's more, there is a clock quality requirement in SPRABI2:

    So to answer your question, the input clock frequency of PASS PLL should in the range of 40~312.5MHz, and the PASS PLL output should be at fixed 350MHz by configuring the PLLM & PLLD field in PASSPLLCTL.register.

    Han

  • 0 in reply to haopeng han
    TI__Guru*** 125430 points

    Han,

    Thank you for taking time to point out those diagrams.  That answers my question.  However it has raised further questions!  I will post separate threads.

    Brad