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AM62A7-Q1: SerDes - how to setup clock "continuous" mode?

Hayden Kim
Genius 15580 points
Part Number: AM62A7-Q1


Champs,

With AM62A custom board, he is testing the camera input with MAX serdes (max9295 -> max96722).

From current Linux SDK (from the k3-am62a7 dts file), it is using as "clock-noncontinuous" driver setting.

port@0 {
	reg = <0>;
	ub953_in: endpoint {
		remote-endpoint = <&sensor_out>;
		data-lanes = <0 1>;
		clock-noncontinuous;
	};
};

Howevere, current using MAX serdes does not support "clock-noncontinuous" mode.

So, he is asking how to modify the driver (dts) to support the MAX serdes which does not support clock-noncontinuous.

Can you please check how to modify the driver not to use "clock-noncontinuous" mode?

Best regards,

Hayden

  • +1
    TI__Guru 59575 points

    Hello Hayden,

    According to UB953 data sheet, bit 6 of General_CFG register configures the CSI-2 clock lane:

    The source code for UB953 driver is drivers/media/i2c/ds90ub953.c. Please check the following function on how the "clock-noncontinuous" entry in device tree is used by the driver:

    static int ub953_general_cfg(struct ub953_data *priv)
{
        struct device *dev = &priv->client->dev;
        u32 num_data_lanes;
        bool clock_continuous;
        int ret;

        ret = of_property_count_u32_elems(priv->rx_ep_np, "data-lanes");
        if (ret < 1 || ret > UB953_MAX_DATA_LANES) {
                dev_err(dev, "DT: invalid data-lanes (%d), only 1-4 lanes supported\n", ret);
                return ret;
        } else {
                num_data_lanes = ret;
        }

        clock_continuous = !of_property_read_bool(priv->rx_ep_np, "clock-noncontinuous");

        return ub953_write(priv, UB953_REG_GENERAL_CFG,
                           ((clock_continuous) << 6) |
                           ((num_data_lanes - 1) << 4) |
                           (1 << 1) | /* CRC TX gen */
                           (priv->use_1v8_i2c << 0));
}

    I believe if you simply remove "clock-noncontinuous" from the device tree, the CSI-2 clock lane will be configured to continuous clock.

    Regards,

    Jianzhong