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McBSP SPI and EDMA

Fred Jaworsky
Prodigy 210 points

I'm using CCS V4.2 and CSL interfacing the C6474L with a custom ADC. The ADC consists of 1 ADC connected to McBSP0 and 2 ADCs connected in series to McBSP1.  ADC Conversion is controlled with a timer output pin. Read operation is controlled by a second timer interrupt with a specific delay following conversion. Reading the single channel is a fairly simple matter with EDMA. The recieve side Param set is using CSL_EDMA3_CHA_REVT0 and the xmit side is controlled by a Param set using a timer event channel. The single channel only requires a single write (EDMA transfer) to DXR for SPI mode to cause the transfer (recieve).

The two channel side introduces a problem. This channel requires three writes to DXR to retrieve all sample bits. The problem in using EDMA by increasing the number of writes fails to wait for DXR to be empty from previous write. While I could use CSL_EDMA3_CHA_XEVT1 instead of a timer to activate the EDMA channel, I would not have control of when the transfer operation is performed. This approach results in a constant on going xmit.

I have considered linking the timer param set to a XEVT1 param set but it appears EDMA is not set up to work this way (not sure). Another possibility would be to add a Timer ISR and Enable the Param set in the ISR for CSL_EDMA3_CHA_XEVT1 then disable it in a TCC ISR. The down side is incurring the overhead of the ISR as the sample rate is increased.

Another possible approach would be to use multiple param sets that perform single writes with each on separate timer, With some trial and error, I should be able to find a balance with sufficient delay between timers for DXR to become empty. 

I have also considered the EDMA3TC RDRATE while increasing the delay for EDMA may solve this problem, it would create more problems for other areas that require EDMA in this application.

Are there any other options or a possible way to use linking?

  • 0
    TI__Guru* 84110 points

    Fred Jaworsky,

    Connecting two devices to McBSP1 "in series" does not sound like the right way to connect the devices. If I understand your post above, you are trying to use the McBSP port in a way that it was not designed to operate.

    My recommendation is to find a compatible multi-channel ADC or add a CPLD to your board that will allow you to control which device is on the bus at any time, perhaps by using a GPIO to select one or the other.

    Please look through the ADC devices available from www.ti.com and find one device to meet your needs that will provide 2 channels or even 3 channels with a single McBSP interface.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 210 points

    RandyP,

    One part of the custom ADC board contains 2 ADC's connected in series as a single digital input (2 channels). They are 18 bit units each so 36 bits need to be read on the McBSP for each sample period. To further complicate matters, the ADC's require a 500ns window following conversion for data to be valid. The board also contains a single ADC for a third channel but it is a single 18 bit channel. This is the board I was given and the task of getting the data.

    McBSP SPI mode appears to be the only choice available for the 6474L that allows software control of when the read operations are performed.

    To control the conversion, I setup a timer routed to the output pin. This signal goes to all ADC's on the custom board for simultaneous sampling.

    For an initial read test of the 2 channel side, I used a second timer to send an interrupt to the CPU. Conversion delay (500ns) is accommodated by adjusting the initial counter values in the timers.Within the ISR for this timer, I write to the DXR then wait for Xmit ready and write a total of 3 times. The McBSP channel is configured for 12 bit SPI operation. EDMA is configured to perform read operations via REVT. Sample rate is controlled by adjusting the timer period. While this test works, it does have limits at higher sample rates due to the handling in an ISR and required polling of DXR.

    At this point, I tried using EDMA to perform the writes to DXR. Since it must be timed correctly, I used one EDMA channel tied to the timer event that linked to a second EDMA channel tied to the XEVT. The idea being that the the first EDMA channel could perform the first xfer to DXR and the linked channel could perform 2 xfers to DXR. This configuration appears to perform one time and I could not determine why the sequence would not continue on each timer event. (Maybe something I missed and not sure where to look for a problem)

    For a more desperate attempt, I setup three EDMA channels each on a separate timer writing to DXR. By monitoring the McBSP CLKX on a scope and adjusting the timer counters, I have each write occurring in sequence. Although not my first choice, It works and the sample rate is substantially higher than ISR could achieve (greater than 600Khz sample rate).

    I still think the option of Timer EDMA linked to XEVT EDMA would be the best fit but not sure of why it would not work.

    Thanks,

    Fred