Background:
We are trying to understand how the firewall on the AM62A works. As a test we created different firewall regions in DDR memory with different permissions. When we read back the regions via the SCI, the following gets reported:
== Firewall configuration dump (1) ==
fwid, region, control, start, end, perm1, perm2, perm3
1, 0, 10a, 80000000, 8ffff000, c3ffff, 8888, 8888
1, 1, a, 90000000, 9003f000, 18d88, 8888, 8888
1, 2, a, 90040000, 9007f000, c3ffff, 8888, 8888
1, 3, a, 90080000, 900bf000, 1ec88, 8888, 8888
1, 4, a, 900c0000, bffff000, c3ffff, 8888, 8888
9, 9, 10a, 3f005000, 4e260000, c3ffff, c3ffff, c3ffff
33, 0, 10a, 0, fffff000, c3ffff, c3ffff, c3ffff
35, 0, 10a, 0, fffff000, c3ffff, c3ffff, c3ffff
160, 0, 10a, 4d000000, 4e3ff000, c3ffff, 8888, 8888
== End of firewall configuration dump (1) ==
This is just a dump of the data send back by the SCI command. The DDR settings (fwid 1) are set by us, the rest of the settings was already present.
DDR is located from 0x8000_0000 - 0xbfff_ffff. Most of memory is accessible by everyone, but two area's have restricted permissions. The area 0x9000_0000 to 0x9003_ffff is set to Non-secure supervisor write and Non-secure supervisor cacheable allowed. Region 0x9008_0000 to 0x900b_ffff is set to Non-secure user read, Non-secure supervisor cacheable and Non-secure user cacheable allowed. Debug allowed for all modes is set automatically by the hardware it seems.
Questions:
- The range specified when setting the region via SCI is different from the one read back. For region 0 0x8fff_ffff get written but 0x8fff_f000 is read back. I assume that this is expected. If region 0 get set to 0x9000_0000 as the end address, setting region 1 fails. Is this correctly understood?
- Is the firewall expected to do anything with these settings? As a test we are reading and writing to the restricted section from both EL0 (user) and EL1 (supervisor) exception modes. All read and write actions succeed independent of what gets allowed by permissions and we expected failures. How can we get an exception from the firewall by accessing DDR illegally? This just for testing purposes, we rely on the MMU for memory protection.
- When we disable the Non-secure supervisor cacheable flag we end up with an exception from the ARM Trusted Firmware:
psci
ERROR: Unhandled External Abort received on 0x80000000 from S-EL1
ERROR: exception reason=1 syndrome=0x92000210
Unhandled Exception from EL1
Why would that happen? The exception handler in EL1 does not get called. Now it is possible to re-configure ATF to not get that exception, but then our RTOS still cannot get it, we were expecting an external abort. Or can TI SCFW be controlled not to generate this exception for ATF, and redirect this elsewhere? If so, how?
4. Is there a complete list of privids for the different masters? We've only found the list of privids in the online TISCI documentation. In the ARM62A TRM we have not found a list of privids.
