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TDA4VM: System time travels faster than real time in SBL boot mode

Part Number: TDA4VM

PSDK version:ti-processor-sdk-rtos-j721e-evm-08_04_00_06 && ti-processor-sdk-linux-j7-evm-08_04_00_11

Hi, When I boot the system in SBL mode,I find that the linux system time travels faster than real time。

What modifications do I need to make to address this issue?

 

System:Linux + RTOS

Boot:tiboot3(SBL)-> can_boot_app_mcu_rtos(MCU1_0) -> lateapp1 

                                                                                                 -> lateapp2

                                                                                                 -> atf_optee.appimage

                                                                                                 -> tikernelimage_linux.appimage

                                                                                                 -> tidtb_linux.appimage

SPL boot mode without MCU1_0, the linux system time is accurate。I check the code, the tick-timer is MCU_TIMER0, and it is configured in tiboot3 (SPL), but SBL mode not use uboot code.

I read linux system time by command 'date',  the system time travels 1 minute faster than the real time every 5 minutes。

  • Hi Frank,

    Can you please share the steps to reproduce the issue?

    Regards,
    Parth

  • Hi Parth,

    I build the images for SBL boot mode.

    Note:
    PSDKLA is the dir for ti-processor-sdk-rtos-j721e-evm-08_04_00_06
    PSDKRA is the dir for ti-processor-sdk-linux-j7-evm-08_04_00_11
    PDK_BUILD_DIR = $(PSDKRA)/pdk_jacinto_*/packages/ti/build

    Build the images for MCU2_0/1 C66_0/1 C71 A72:
    make -C $PSDKLA all
    make -C $PSDKRA/vision_apps sdk

    Build SBL image:
        make -C $(PDK_BUILD_DIR) BOARD=j721e_evm SOC=j721e CORE=mcu1_0 BUILD_PROFILE=release pdk_libs
        make -C $(PDK_BUILD_DIR) BOARD=j721e_evm SOC=j721e CORE=mcu1_0 BUILD_PROFILE=release DISABLE_RECURSE_DEPS=no sbl_cust_img
    Images:
        $(PDK_DIR)/packages/ti/boot/sbl/binary/j721e_evm/cust/bin/sbl_cust_img_mcu1_0_release.tiimage
        $(PDK_DIR)/packages/ti/drv/sciclient/soc/V1/tifs.bin
        $(PDK_DIR)/packages/ti/board/src/flash/nor/ospi/nor_spi_patterns.bin


    Build Can Boot app:
        make -C $PSDKRA/vision_apps sbl_mcusw_bootimage_ospi
    Images:
        $PSDKRA/vision_apps/out/sbl_bootfiles/can_boot_app_mcu_rtos_mcu1_0_release_ospi.appimage

    Convert images format for A72:
        cd $PSDKRA/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/
        ./constructappimageshlos.sh j721e_evm
    Images:
        atf_optee.appimage
        tidtb_linux.appimage
        tikernelimage_linux.appimage

    Packaging images for MCU2_0/1 C66_0/1 and C71:
    make -C $PSDKRA/vision_apps sbl_vision_apps_bootimage
    Images:
    $PSDKRA/vision_apps/out/sbl_bootfiles/lateapp1
    $PSDKRA/vision_apps/out/sbl_bootfiles/lateapp2


    Then, Flash the images into OSPI Flash, boot the system from OSPI.
    Wait for the system bring up, synchronize board time and PC time by command 'date'.
    Wait for 5 minutes and get the board system time by 'date', and compare it to PC time.

  • Hi Parth,

    Do you have any new information to provide?

    Or do you need me to provide any information?

    I reproduce the problem on EVM by SPL boot mode if I enable  MCU1_0 in PSDKRA.

  • Hi Frank,

    Apologies for delay in response.

    I reproduce the problem on EVM by SPL boot mode if I enable  MCU1_0 in PSDKRA.

    What do you mean by enable MCU1_0 is SPL boot mode? Are you telling you are seeing this issue with SPL boot flow as well?

    Regards,
    Parth

  • Hi Parth,

    What do you mean by enable MCU1_0 is SPL boot mode? Are you telling you are seeing this issue with SPL boot flow as well?

    Yes, I reproduce the issue with SPL boot if I set BUILD_CPU_MCU1_0=yes in psdkra/vision_apps/vision_apps_build_flags.mak before compiling PSDKRA.

    I check the diffrence is the MCU1_0 image in tispl.bin:

    when BUILD_CPU_MCU1_0=no, DM=psdkla/board-support/prebuilt-images/ipc_echo_testb_mcu1_0_release_strip.xer5f  (psdkla/Makefile line 276)

    when BUILD_CPU_MCU1_0=yes,  DM= psdkra/vision_apps/out/J7/R5F/FREERTOS/release/vx_app_rtos_linux_mcu1_0_strip.out

     

  • Hi Parth,

    Any update?

  • Hi Frank,

    This seems to be have fell through the cracks.
    Is support still required on this?

    If yes, can you please check the GTC clock frequency being set in SBL and SPL?

    Regards,
    Parth