AM625: Query reg RMII Internal clock configuration

Hello Premalatha Royappan

Thank you for the note.

Please separate the boot question into another thread to avoid delay in response.

Premalatha Royappan said:

• Also its mentioned that its recommended to to provide provision for external clock source although Internal clock configuration is provided. We haven't provided any such provision on our board. Please let us know if this is essential to have such a provision.

Please share the recommendations we have made to use internal clock.

Premalatha Royappan said:

• Also its mentioned that its recommended to to provide provision for external clock source although Internal clock configuration is provided. We haven't provided any such provision on our board. Please let us know if this is essential to have such a provision.

This is a just in case option if the internal clock performance does not meet the performance requirement.

Regards,

Sreenivasa

Hello Premalatha Royappan

Please share the recommendations TI made on using the internal clock.

Kallikuppa Sreenivasa said:

• Also its mentioned that its recommended to to provide provision for external clock source although Internal clock configuration is provided. We haven't provided any such provision on our board. Please let us know if this is essential to have such a provision.

Please share the recommendations we have made to use internal clock.

Regards,

Sreenivasa

Hi Sreenivasa,

Updates regarding my 3 queries,

1. I have raised a separate e2e request for Ethernet boot.
2. Regarding recommendation for internal clock source:, This was discussed in one of our calls with TI after which TI recommended to use Internal clock source for RMII for better performance. We want to understand if there are any concerns with Internal clock source as the recent schematics checklist document mentions recommending External clock source.
3. Please let us know if the CLKOUT signal from the processor can be used for RMII clocking? Are there any performance limitations to this? We want to know this because providing a external clock source option in addition to internal clock source complicates routing of clock signals.

Hello Premalatha Royappan

Thank you for the inputs.

Before i could answer the query, please help me understand the below. 

Are you using the clock output of the PHY configuring the PHY as master (25M clock to Xi and 50M clock output) as the SoC clock input or are you using the SoC clock output - 50M connected to both the PHY and the SoC.

Can you pls draw a diagram for me to understand.

Regards,

Sreenivasa

Hi Sreenivasa

Below is our implementation, using the SoC clock output - 50M connected to both the PHY and the SoC.

Hello Premalatha Royappan

Thank you for the inputs.

Can you help me understand the clock that you are referring as sync clock where you are talking about matching data and clock length?

Regards,

Sreenivasa

Hi Sreenivasa

Kindly let us know if there are any concerns with our RMII clock implementation.

Regarding your query about matching lengths, we have matched the clocks going to the PHY and MAC(processor) along with their respective channel  RMII TX/RX signals. Same color coding is given for those which are length matched in the below snapshot.Length matching within 2 inches followed as per AN-1469. Please let us know if there are any concerns to this implementation.

Hello Premalatha Royappan

Thank you for the note.

Premalatha Royappan said:

Regarding your query about matching lengths, we have matched the clocks going to the PHY and MAC(processor) along with their respective channel  RMII TX/RX signals.

Please review the RMII specs and functionality.

Please review the PHY AC timings, RMII timings for the SoC in the datasheet and also do a timing calculation.

Pls note the TX (PHY - receive) and TX (SoC - transmit) terminology.

You should also ask for clarification regarding AN-1469 recommendations from the Ethernet PHY team.

Regards,

Sreenivasa

Hi Sreenivasa

The below is the email we received from TI recommending Internal clock configuration for RMII.Also I have attached snapshots of the discussion which happened during the TI call for choosing this clock configuration.

Hello Premalatha Royappan

Thank you for the inputs.

Q.1 Using PHY clock vs SoC clock

The recommendation seems to be between using 50M from the PHY vs using 50M from the SoC (the one with lower risk).

I am trying to understand the concern you have

The preferred approach for RMII interface is to configure the PHY as slave and to use an external clock for the SoC/PHY.

It is acceptable for Customer to use SoC internal clock and connect to the RMII interface of PHY and SoC provided customer understand the validation challenges.

We recommend provisioning for an external clock as fallback option in case the internal clock performance does not match the requirement.

Q.2 Clock routing from the buffer 

In the picture that has red text, i see the guidelines to place the clock at the middle of the PHY and the SoC which results in 1/2 the TX/RX signal length. 

I am trying to understand the reason you matched the clocks to the TX/RX lines for RMII interface and is acceptable if you have done the required timing analysis. 

Customers are of course free to implement clocking topologies as they see fit, but they will need to accept the inherent risk in doing so.

Regards.

Sreenivasa

Hi Sreenivasa,

Below is the implementation we have done w.r.t RMII length matching.

• Equal length clock traces from the clock buffer to MAC and PHY is implemented to the extend possible with minimal deviation. However w.r.t External card we couldn't follow equal trace length and hence we are doubtful if there could be any timing violation.
• Clock traces are not exactly 50% w.r.t data lines. However we have tried as much as possible

We are facing hold time failure with this implementation. Kindly provide suggestions to achieve the hold time requirement of 2ns.

Hello Premalatha, 

Thank you.

I am not familiar with the simulating environment you are using and so not sure what suggestions i can give. I would say to a hand calculation.

Please help me understand what the waveform is representing.

Premalatha Royappan said:

We are facing hold time failure with this implementation.

Where is the problem - At the SoC or at the PHY?

I am not a simulation or Ethernet expert.  I need to reach out to the experts internally. I have a few questions.

If the issues are with the PHY timing, the PHY team can help.

Have you done a quick hand calculation on the expected delay before simulating to confirm there is margin in the design.

I will have to check internally with the Ethernet expert based on the details you provide.

I saw a mail from Stuart suggesting you reduce the RMII data signals length. I did not see the length information in the diagram you have.

Are you adding the SODIMM connector delay?

Have you tried simulating without the connector delay?

Regards,

Sreenivasa

Hi Sreenivasa,

We have the lengths mentioned in mils in this diagram below which I had shared previously. And yes, we are considering the SODIMM connector delay also in our simulation.

For a hand calculation:  50MHZ external clock source (20ns time period)

**********************************************************

When AM625X is transmitting and PHY receiving

***********************************************************

The clock to output delay from AM625x is from 2n to 10ns max. At the PHY side the setup and hold time requirement is 4ns/2ns (PHY : DP83620SQE)

The clock length  is 3500mils approx( assuming 170ps/inch propagation delay) delay due to length of the trace = 0.595ns

The data signal length is 6000 mils approx ,hence delay due to length of the trace = 1.02ns. Timing looks fine.

**********************************************************

When PHY is transmitting and AM625x receiving

**********************************************************

The clock to output delay is from PHY is 2n to 14ns max. At the processor side the setup and hold time requirement is 4ns/2ns

Please let us know any issues w.r.t timing as we are not observing issue in theoretical calculations as per the above details.

Hello Premalatha, 

Thank you for the inputs.

Are expecting to have 2n to 14ns max delay on a 20ns clock period?

Kallikuppa Sreenivasa said:

Have you tried simulating without the connector delay?

Do you have the calculation and required margin without the connector delay added.

Regards,

Sreenivasa