Looking for confirmation if the M4 can access the DDR memory? How is that managed?
Hi Lawrence,
I have attached below a sample CCS Hello World example for M4F core that writes a known data (1 to 1000 numbering) to DDR
In this example, a RAT entry is added to map the initial 256MB memory of DDR to the M4F core's local 32b memory address space. The below image shows the RAT entry added
Please note the DDR is available system wide at 0x80000000 only. However, the above RAT entry makes the M4F core see the DDR from the base address 0x90000000. So, the example uses 0x90000000 as the base address to access DDR.
Now, to verify that M4F core indeed writes the data to DDR, we can connect to A53 and read the address 0x80000000 from the CCS Memory Browser as shown
Regards,
Prashant
