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AM625: SDIO_CLK quality check

Part Number: AM625

On customer board, connect MMC2 with WIFI module via serial inductance to eliminate overshot, probe on inductance of AM62 side, the clock signal has some reflection on edge, on WIFI side, the rising/falling edge is clean, we think on WIFI side should be OK, will the AM62 side clock quality impact AM62 SDIO receiving data?

In other word, as the SDIO_CLK is a output signal, will AM62 MMC use the external clock for receiving?