TDA4VM: SCICLIENT: ERROR: Sciclient_pmSetModuleClkFreq failed

Hi henry wu,

Does it work fine without warm reset? can you please share the code where you are setting this clock? We probably need to change the way to setup the clock.

Regards,

Brijesh

Hi  Brijesh,

1. Does it work fine without warm reset? 

[A] yes

2. Code snippets (TI source code)

<vision_apps/utils/dss/src/app_dss_j721e.c> appDssConfigurePm

    else if(prm->display_type==APP_DSS_DEFAULT_DISPLAY_TYPE_DPI_HDMI)
    {   
        /*  
     * initialize PLL for VP1
     *
     * Summary:
     * VP1 pclk must come from PLL19 (for our EVM) because
     * we are routing VP1's output to DPI0, which is retimed
     * using PLL19 HSDIV0 output.
     * Therefore, set parent to PLL19 HSDIV0 and then set rate
     * to 148.5 MHz
     */
        SET_CLOCK_PARENT(TISCI_DEV_DSS0, TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK, TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0);
        SET_CLOCK_FREQ (TISCI_DEV_DSS0, TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK, prm->timings.pixelClock);
        SET_CLOCK_STATE(TISCI_DEV_DSS0, TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK, 0, TISCI_MSG_VALUE_CLOCK_SW_STATE_REQ);
    }  

BR

Hi Brijesh,

Could you give some suggestions?

Thanks

hi henry wu,

Is it possible to recreate this issue on EVM? Can you please share the steps on EVM? 

What i want to do is to enable TIFS logging and see why TIFS is not able to set the clock. 

Regards,

Brijesh

Btw, i have been trying to recreate this issue on EVM with SDK8.6 release, but unable to recreate it so. I have tried warm reset (reboot from Linux prompt) for 700+ times, but clock settings for HDMI output is always successful. 

Regards,

Brijesh

Hi Brijesh,

May you try to MCU warm reset（k3conf read  0x43000050， Bit0 is set）.We reproduce this issue  when system trigger MCU warm reset

Thanks

Hi Henry wu,

But how do you trigger MCU warm reset? This register just provides the status of the SW reset..

Regards,

Brijesh