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TDA4VH-Q1: DDRSS supported configuration and TRM DDR mapping informations

John Doe7
Intellectual 360 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Hi,

The TI DDRSS configuration tool (SPRACU8B_Jacinto7_DDRSS_RegConfigTool.xlsb version 0.10.0) seems to limit the described options in the TRM (SPRUJ52B – JUNE 2022 – REVISED NOVEMBER 2022) to the following configurations :

  • b0001 - EMIF 0 Active      (DDRSS0)
  • b0011 - EMIF 0,1 Active   (DDRSS0 & DDRSS1)
  • b0111 - EMIF 0,1,2 Active (DDRSS0, DDRSS1 & DDRSS2)
  • b1111 - EMIF 0,1,2,3 Active  (DDRSS0, DDRSS1,DDRSS2 & DDRSS3)

Is an updated configuration tool planned to allow for non consecutive DDRSS usage (for example DDRSS1 and DDRSS3 usage only) ?

In the TRM, for the upper DDR mapping (from 0x08_0000_0000 to 0x10_0000_0000) is seems the first 2GB are inaccessible because already mapped in the 32bit address space ( from 0x00_8000_0000 to 0x01_0000_0000). What is the expected behavior if a memory access is performed in that range ?

In the TRM, the DDRSS mapping lines seems to be duplicated since two entries with the same memory addresses exists :

  • NAVSS0_DDR0_MEM and NAVSS0_DDR1_MEM (from 0x00_8000_0000 to 0x01_0000_0000)
  • NAVSS0_DDR0_MEM1 and NAVSS0_DDR1_MEM1 (from 0x08_0000_0000 to 0x10_0000_0000)

Could you confirm this is an error in the TRM ?

Best regards

  • +1
    TI__Mastermind 38440 points

    Hi,

    John Doe7 said:
    Is an updated configuration tool planned to allow for non consecutive DDRSS usage (for example DDRSS1 and DDRSS3 usage only) ?

    No, the DDRSS must be used in order for TDA4VH. 

    John Doe7 said:
    In the TRM, for the upper DDR mapping (from 0x08_0000_0000 to 0x10_0000_0000) is seems the first 2GB are inaccessible because already mapped in the 32bit address space ( from 0x00_8000_0000 to 0x01_0000_0000). What is the expected behavior if a memory access is performed in that range ?

    It is correct that the first 2GB of the upper 32GB region is inaccessible (cannot be used). This address space does not map to external DDR and is non-functional. 

    John Doe7 said:

    In the TRM, the DDRSS mapping lines seems to be duplicated since two entries with the same memory addresses exists :

    • NAVSS0_DDR0_MEM and NAVSS0_DDR1_MEM (from 0x00_8000_0000 to 0x01_0000_0000)
    • NAVSS0_DDR0_MEM1 and NAVSS0_DDR1_MEM1 (from 0x08_0000_0000 to 0x10_0000_0000)

    Could you confirm this is an error in the TRM ?

    Agree, the main memory map table is a bit confusing. I believe it was written that way to illustrate that accesses in those spaces could be mapped to either DDRSS0 or DDRSS1 when interleaved. (the TRM would then be missing DDRSS2 & DDRSS3 entries).

    I personally find the rows illustrated in Table 8-6 (MSMC Memory Regions) a bit more fitting. Specifically, there are 2 different sections that map to DDR memory. The exact mapping to which DDRSS (1,2,3,4) depends on interleave settings. 

    Regards,
    Kevin