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TDA4VH-Q1: NAVSS (MAIN & MCU) interrupt routers

John Doe7
Intellectual 360 points

Part Number: TDA4VH-Q1

Hi,

I was not able to find documentation in the TRM (SPRUJ52B – JUNE 2022 – REVISED NOVEMBER 2022) or the SDK (PROCESSOR-SDK-RTOS-J784S4 — RTOS SDK version 08.06.00.14) the needed information to configure the INTRTR and INTA interrupt routers. Could you provide examples and associated register documentation ?

Best regards

  • 0
    TI__Genius 17216 points

    The interrupt router register definitions are included in the XLS that is provided along side the PDF in the TRM zip file. The mappings for the MUX_CNTL fields of the registers can be found in the Interrupt Sources chapter of the TRM PDF.

    Note that the interrupt register definition in the XLS currently has a couple of limitations:

    • It only shows the address for the first INTRTR_muxcntl_n register (i.e. n=0), which controls output 0 of the mux. The register that controls output 1 of the mux is +4h offset from the mux 0 registers, and so on for all output of the mux.
    • The field width of the MUX_CTRL field is not accurate in all cases. The width of this field varies and corresponds to the number of bits required to select from all of the possible mux inputs described in the Interrupt Sources chapter tables.

    The register XLS will be updated in a future revision to correct these issues.

    Regarding how these registers function, see TRM section "INTRTR Overview".