AM625: Configure AUDIO_EXT_REFCLK1

Isee

Part Number: AM625

What is the correct way to enable a clock output on AUDIO_EXT_REFCLK1 pin?

We do have GPMC0_WPn (K25) pin that we would like to have it enabled and output a clock. From some old discussions it should be possible to have a 25MHz clock there.

over 2 years ago

0 Suren Porwar over 2 years ago

TI__Mastermind 28995 points

Hi Isee,

I am talking internally with the team on enabling clock on AUDIO_EXT_REFCLK1. Will get back to you as soon as I have an update.

In the meantime, can you please share the k3conf dump clocks | grep AUDIO_EXT_REFLCK1 from the EVM with your DT changes in place.

Thanks

Suren

0 Isee over 2 years ago in reply to Suren Porwar

TI__Expert 6650 points

I found out that if I manually set the AUDIO_REFCLK1 to be output rather than the default input via CTRL_AUDIO_REFCLK1_CTRL register (Offset = 82E4h resp. 0x1082E4) bit 15 AUDIO_REFCLK1_CTRL_CLKOUT_EN (see section 6.1.1.3.1.160.1 CTRL_AUDIO_REFCLK1_CTRL Register on page 2688 of the latest TRM called SPRUIV7, https://www.ti.com/lit/pdf/SPRUIV7) it actually starts working. I did that via a utility called devmem2 which allows us to set arbitrary values at arbitrary memory/register addresses as follows:

root@verdin-am62-14917624:~# devmem2 0x001082E4 w 0x00008007
2/dev/mem opened.
3Memory mapped at address 0xffff900f5000.
4Read at address 0x001082E4 (0xffff900f52e4): 0x00000007
5Write at address 0x001082E4 (0xffff900f52e4): 0x00008007, readback 0x00008007

However, as the entire clock handling is done in TI’s proprietary system controller accessed from the Linux kernel only via TI SCI protocol, we have to assume this is actually a bug in that exact system controller implementation.

BTW: Here is the link to the documented clocks ( https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html ) and as @Francesco Dolcini pointed out above we are indeed using device AM62X_DEV_BOARD0 with an ID of 157 and the DEV_BOARD0_AUDIO_EXT_REFCLK1_IN with a clock ID of 10 which should indeed be the clock we are looking for. Maybe the input vs. output nomenclature was too confusing even for TI’s own engineers .

Can you please confirm this or suggest how exactly this is supposed to work? Thanks!

We are working on the dumbs that you asked for.

0 Isee over 2 years ago in reply to Isee

TI__Expert 6650 points

Please find attached two full k3conf dump clocks one with 24.576 MHz (outputting 24.3901 MHz as verified by our HW folks) and the other one with 25 MHz. They were taken on our own Hardware (we do have the k3conf integrated into our BSP as well).

id="fragment-1a84591e31034fac832d29ed8584666c1300675687_code-editor-fs">Fullscreen href="https://e2e.ti.com/cfs-filesystemfile/__key/communityserver-discussions-components-files/791/k3conf_2D00_dump_2D00_clock_2D00_157.log?_=638168948520000000" title="Download k3conf-dump-clock-157.log">k3conf-dump-clock-157.log href="https://e2e.ti.com/cfs-filesystemfile/__key/communityserver-discussions-components-files/791/k3conf_2D00_dump_2D00_clock_2D00_157.log?_=638168948520000000" title="Download k3conf-dump-clock-157.log">Download t-1a84591e31034fac832d29ed8584666c1300675687_code-editor" ht:240px;min-width:320px;margin:0px;" ="true">|--------------------------------------------------------------------------------| | --------------------------------------------------------------| (version v0.1-64-g48cb8e8 built Tue 04 Apr 2023 06:45:36 PM UTC) | | ABI: 3.1 (firmware version 0x0008 '8.5.3--v08.05.03 (Chill Capybar)') | --------------------------------------------------------------| neric_fprint(): WARNING: "DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLKCLK_STATE_READY" size (115) > TABLE_MAX_ELT_LEN (100)! ---------------------------------------------------------------------------------------------------------------------------------------------------| | Clock ID | Clock Name | Status | Clock Frequency | ---------------------------------------------------------------------------------------------------------------------------------------------------| 0 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN | CLK_STATE_READY | 24390243 | 1 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_NOT_READY | 0 | 2 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_NOT_READY | 0 | 3 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_NOT_READY | 0 | 4 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_NOT_READY | 0 | 5 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_NOT_READY | 0 | 6 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_NOT_READY | 0 | 7 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY | 96000000 | 8 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK | CLK_STATE_READY | 24390243 | 9 | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | 10 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN | CLK_STATE_READY | 24390243 | 11 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_NOT_READY | 0 | 12 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_NOT_READY | 0 | 13 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_NOT_READY | 0 | 14 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_NOT_READY | 0 | 15 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_NOT_READY | 0 | 16 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_NOT_READY | 0 | 17 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY | 96000000 | 18 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK | CLK_STATE_READY | 24390243 | 19 | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | 20 | DEV_BOARD0_CLKOUT0_IN | CLK_STATE_READY | 25000000 | 21 | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5 | CLK_STATE_READY | 50000000 | 22 | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10 | CLK_STATE_READY | 25000000 | 23 | DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | 24 | DEV_BOARD0_DDR0_CK0_IN | CLK_STATE_READY | 250000000 | 25 | DEV_BOARD0_DDR0_CK0_N_IN | CLK_STATE_READY | 0 | 27 | DEV_BOARD0_DDR0_CK0_OUT | CLK_STATE_READY | 0 | 33 | DEV_BOARD0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | 34 | DEV_BOARD0_GPMC0_CLKLB_IN | CLK_STATE_READY | 0 | 35 | DEV_BOARD0_GPMC0_CLKLB_OUT | CLK_STATE_READY | 0 | 36 | DEV_BOARD0_GPMC0_CLK_IN | CLK_STATE_READY | 0 | 37 | DEV_BOARD0_GPMC0_FCLK_MUX_IN | CLK_STATE_READY | 133333333 | 38 | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK | CLK_STATE_READY | 133333333 | 39 | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK | CLK_STATE_READY | 100000000 | 40 | DEV_BOARD0_I2C0_SCL_IN | CLK_STATE_READY | 0 | 41 | DEV_BOARD0_I2C0_SCL_OUT | CLK_STATE_READY | 0 | 42 | DEV_BOARD0_I2C1_SCL_IN | CLK_STATE_READY | 0 | 43 | DEV_BOARD0_I2C1_SCL_OUT | CLK_STATE_READY | 0 | 44 | DEV_BOARD0_I2C2_SCL_IN | CLK_STATE_READY | 0 | 45 | DEV_BOARD0_I2C2_SCL_OUT | CLK_STATE_READY | 0 | 46 | DEV_BOARD0_I2C3_SCL_IN | CLK_STATE_READY | 0 | 47 | DEV_BOARD0_I2C3_SCL_OUT | CLK_STATE_READY | 0 | 49 | DEV_BOARD0_MCASP0_ACLKR_IN | CLK_STATE_READY | 0 | 50 | DEV_BOARD0_MCASP0_ACLKR_OUT | CLK_STATE_READY | 0 | 51 | DEV_BOARD0_MCASP0_ACLKX_IN | CLK_STATE_READY | 0 | 52 | DEV_BOARD0_MCASP0_ACLKX_OUT | CLK_STATE_READY | 0 | 53 | DEV_BOARD0_MCASP0_AFSR_IN | CLK_STATE_READY | 0 | 54 | DEV_BOARD0_MCASP0_AFSX_IN | CLK_STATE_READY | 0 | 55 | DEV_BOARD0_MCASP1_ACLKR_IN | CLK_STATE_READY | 0 | 56 | DEV_BOARD0_MCASP1_ACLKR_OUT | CLK_STATE_READY | 0 | 57 | DEV_BOARD0_MCASP1_ACLKX_IN | CLK_STATE_READY | 0 | 58 | DEV_BOARD0_MCASP1_ACLKX_OUT | CLK_STATE_READY | 0 | 59 | DEV_BOARD0_MCASP1_AFSR_IN | CLK_STATE_READY | 0 | 60 | DEV_BOARD0_MCASP1_AFSX_IN | CLK_STATE_READY | 0 | 61 | DEV_BOARD0_MCASP2_ACLKR_IN | CLK_STATE_READY | 0 | 62 | DEV_BOARD0_MCASP2_ACLKR_OUT | CLK_STATE_READY | 0 | 63 | DEV_BOARD0_MCASP2_ACLKX_IN | CLK_STATE_READY | 0 | 64 | DEV_BOARD0_MCASP2_ACLKX_OUT | CLK_STATE_READY | 0 | 65 | DEV_BOARD0_MCASP2_AFSR_IN | CLK_STATE_READY | 0 | 66 | DEV_BOARD0_MCASP2_AFSX_IN | CLK_STATE_READY | 0 | 67 | DEV_BOARD0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | 68 | DEV_BOARD0_MCU_I2C0_SCL_IN | CLK_STATE_READY | 0 | 69 | DEV_BOARD0_MCU_I2C0_SCL_OUT | CLK_STATE_READY | 0 | 70 | DEV_BOARD0_MCU_OBSCLK0_IN | CLK_STATE_READY | 12500000 | 71 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 | CLK_STATE_READY | 12500000 | 72 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 25000000 | 73 | DEV_BOARD0_MCU_SPI0_CLK_IN | CLK_STATE_READY | 0 | 75 | DEV_BOARD0_MCU_SPI1_CLK_IN | CLK_STATE_READY | 0 | 77 | DEV_BOARD0_MCU_SYSCLKOUT0_IN | CLK_STATE_READY | 100000000 | 78 | DEV_BOARD0_MCU_TIMER_IO0_IN | CLK_STATE_READY | 0 | 79 | DEV_BOARD0_MCU_TIMER_IO1_IN | CLK_STATE_READY | 0 | 80 | DEV_BOARD0_MCU_TIMER_IO2_IN | CLK_STATE_READY | 0 | 81 | DEV_BOARD0_MCU_TIMER_IO3_IN | CLK_STATE_READY | 0 | 82 | DEV_BOARD0_MDIO0_MDC_IN | CLK_STATE_READY | 0 | 83 | DEV_BOARD0_MMC0_CLKLB_IN | CLK_STATE_READY | 0 | 84 | DEV_BOARD0_MMC0_CLKLB_OUT | CLK_STATE_READY | 0 | 86 | DEV_BOARD0_MMC0_CLK_OUT | CLK_STATE_READY | 0 | 87 | DEV_BOARD0_MMC1_CLKLB_IN | CLK_STATE_READY | 0 | 88 | DEV_BOARD0_MMC1_CLKLB_OUT | CLK_STATE_READY | 0 | 89 | DEV_BOARD0_MMC1_CLK_IN | CLK_STATE_READY | 0 | 90 | DEV_BOARD0_MMC1_CLK_OUT | CLK_STATE_READY | 0 | 91 | DEV_BOARD0_MMC2_CLKLB_IN | CLK_STATE_READY | 0 | 92 | DEV_BOARD0_MMC2_CLKLB_OUT | CLK_STATE_READY | 0 | 93 | DEV_BOARD0_MMC2_CLK_IN | CLK_STATE_READY | 0 | 94 | DEV_BOARD0_MMC2_CLK_OUT | CLK_STATE_READY | 0 | 95 | DEV_BOARD0_OBSCLK0_IN | CLK_STATE_READY | 500000000 | 96 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK | CLK_STATE_READY | 500000000 | 97 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK | CLK_STATE_READY | 192000000 | 98 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | CLK_STATE_READY | 333333333 | 99 | DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK | CLK_STATE_READY | 0 | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK | CLK_STATE_READY | 400000000 | | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT | CLK_STATE_READY | 12500000 | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 | CLK_STATE_READY | 30637 | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 | CLK_STATE_READY | 500000000 | | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 25000000 | | DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK0_MUX_SEL_DIV_CLKOUT | CLK_STATE_READY | 32552 | | DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 | CLK_STATE_READY | 0 | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK | CLK_STATE_READY | 400000000 | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 400000000 | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 1190000000 | | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 170000000 | | DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | DEV_BOARD0_OBSCLK0_IN_PARENT_CLK_32K_RC_SEL_OUT0 | CLK_STATE_READY | 32768 | | DEV_BOARD0_OSPI0_DQS_OUT | CLK_STATE_READY | 0 | | DEV_BOARD0_OSPI0_LBCLKO_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_OSPI0_LBCLKO_OUT | CLK_STATE_READY | 0 | | DEV_BOARD0_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | DEV_BOARD0_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_RGMII1_TXC_OUT | CLK_STATE_READY | 0 | | DEV_BOARD0_RGMII2_RXC_OUT | CLK_STATE_READY | 0 | | DEV_BOARD0_RGMII2_TXC_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_RGMII2_TXC_OUT | CLK_STATE_READY | 0 | | DEV_BOARD0_RMII1_REF_CLK_OUT | CLK_STATE_READY | 0 | | DEV_BOARD0_RMII2_REF_CLK_OUT | CLK_STATE_READY | 0 | | DEV_BOARD0_SPI0_CLK_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_SPI1_CLK_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_SPI2_CLK_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_SYSCLKOUT0_IN | CLK_STATE_READY | 125000000 | | DEV_BOARD0_TCK_OUT | CLK_STATE_READY | 0 | | DEV_BOARD0_TIMER_IO0_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_TIMER_IO1_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_TIMER_IO2_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_TIMER_IO3_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_TIMER_IO4_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_TIMER_IO5_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_TIMER_IO6_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_TIMER_IO7_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_TRC_CLK_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT | CLK_STATE_READY | 0 | | DEV_BOARD0_VOUT0_PCLK_IN | CLK_STATE_READY | 0 | | DEV_BOARD0_WKUP_CLKOUT0_IN | CLK_STATE_READY | 25000000 | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 25000000 | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_LFOSC0_CLKOUT | CLK_STATE_READY | 32768 | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK | CLK_STATE_READY | 50000000 | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_CLK_32K_RC_SEL_OUT0 | CLK_STATE_READY | 32768 | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT | CLK_STATE_READY | 12500000 | | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0 | CLK_STATE_READY | 25000000 | ---------------------------------------------------------------------------------------------------------------------------------------------------| = j('#fragment-1a84591e31034fac832d29ed8584666c1300675687_code-editor-fs'); = j('#fragment-1a84591e31034fac832d29ed8584666c1300675687_code-editor'); function(){ (codeEditor.evolutionCodeEditor('fullscreen')) { codeEditor.evolutionCodeEditor('fullscreen', false); codeEditor.evolutionCodeEditor('fullscreen', true);

Fullscreen k3conf-dump-clock-157-25.log Download

|--------------------------------------------------------------------------------|
| VERSION INFO                                                                   |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-64-g48cb8e8 built Tue 04 Apr 2023 06:45:36 PM UTC)      |
| SoC    | AM62X SR1.0                                                           |
| SYSFW  | ABI: 3.1 (firmware version 0x0008 '8.5.3--v08.05.03 (Chill Capybar)') |
|--------------------------------------------------------------------------------|

autoadjust_table_generic_fprint(): WARNING: "DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLKCLK_STATE_READY" size (115) > TABLE_MAX_ELT_LEN (100)!
|---------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                                                           | Status              | Clock Frequency |
|---------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|   157     |     0    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                                                      | CLK_STATE_READY     | 25000000        |
|   157     |     1    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |     2    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |     3    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |     4    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |     5    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |     6    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |     7    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK                           | CLK_STATE_READY     | 96000000        |
|   157     |     8    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK                            | CLK_STATE_READY     | 25000000        |
|   157     |     9    | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                                                     | CLK_STATE_READY     | 0               |
|   157     |    10    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                                                      | CLK_STATE_READY     | 25000000        |
|   157     |    11    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |    12    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |    13    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |    14    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |    15    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |    16    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT                                | CLK_STATE_NOT_READY | 0               |
|   157     |    17    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK                           | CLK_STATE_READY     | 96000000        |
|   157     |    18    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK                            | CLK_STATE_READY     | 25000000        |
|   157     |    19    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                                                     | CLK_STATE_READY     | 0               |
|   157     |    20    | DEV_BOARD0_CLKOUT0_IN                                                                                | CLK_STATE_READY     | 25000000        |
|   157     |    21    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5                                      | CLK_STATE_READY     | 50000000        |
|   157     |    22    | DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10                                     | CLK_STATE_READY     | 25000000        |
|   157     |    23    | DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT                                                                | CLK_STATE_READY     | 0               |
|   157     |    24    | DEV_BOARD0_DDR0_CK0_IN                                                                               | CLK_STATE_READY     | 250000000       |
|   157     |    25    | DEV_BOARD0_DDR0_CK0_N_IN                                                                             | CLK_STATE_READY     | 0               |
|   157     |    27    | DEV_BOARD0_DDR0_CK0_OUT                                                                              | CLK_STATE_READY     | 0               |
|   157     |    33    | DEV_BOARD0_EXT_REFCLK1_OUT                                                                           | CLK_STATE_READY     | 0               |
|   157     |    34    | DEV_BOARD0_GPMC0_CLKLB_IN                                                                            | CLK_STATE_READY     | 0               |
|   157     |    35    | DEV_BOARD0_GPMC0_CLKLB_OUT                                                                           | CLK_STATE_READY     | 0               |
|   157     |    36    | DEV_BOARD0_GPMC0_CLK_IN                                                                              | CLK_STATE_READY     | 0               |
|   157     |    37    | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                                                         | CLK_STATE_READY     | 133333333       |
|   157     |    38    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK                                | CLK_STATE_READY     | 133333333       |
|   157     |    39    | DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK                               | CLK_STATE_READY     | 100000000       |
|   157     |    40    | DEV_BOARD0_I2C0_SCL_IN                                                                               | CLK_STATE_READY     | 0               |
|   157     |    41    | DEV_BOARD0_I2C0_SCL_OUT                                                                              | CLK_STATE_READY     | 0               |
|   157     |    42    | DEV_BOARD0_I2C1_SCL_IN                                                                               | CLK_STATE_READY     | 0               |
|   157     |    43    | DEV_BOARD0_I2C1_SCL_OUT                                                                              | CLK_STATE_READY     | 0               |
|   157     |    44    | DEV_BOARD0_I2C2_SCL_IN                                                                               | CLK_STATE_READY     | 0               |
|   157     |    45    | DEV_BOARD0_I2C2_SCL_OUT                                                                              | CLK_STATE_READY     | 0               |
|   157     |    46    | DEV_BOARD0_I2C3_SCL_IN                                                                               | CLK_STATE_READY     | 0               |
|   157     |    47    | DEV_BOARD0_I2C3_SCL_OUT                                                                              | CLK_STATE_READY     | 0               |
|   157     |    49    | DEV_BOARD0_MCASP0_ACLKR_IN                                                                           | CLK_STATE_READY     | 0               |
|   157     |    50    | DEV_BOARD0_MCASP0_ACLKR_OUT                                                                          | CLK_STATE_READY     | 0               |
|   157     |    51    | DEV_BOARD0_MCASP0_ACLKX_IN                                                                           | CLK_STATE_READY     | 0               |
|   157     |    52    | DEV_BOARD0_MCASP0_ACLKX_OUT                                                                          | CLK_STATE_READY     | 0               |
|   157     |    53    | DEV_BOARD0_MCASP0_AFSR_IN                                                                            | CLK_STATE_READY     | 0               |
|   157     |    54    | DEV_BOARD0_MCASP0_AFSX_IN                                                                            | CLK_STATE_READY     | 0               |
|   157     |    55    | DEV_BOARD0_MCASP1_ACLKR_IN                                                                           | CLK_STATE_READY     | 0               |
|   157     |    56    | DEV_BOARD0_MCASP1_ACLKR_OUT                                                                          | CLK_STATE_READY     | 0               |
|   157     |    57    | DEV_BOARD0_MCASP1_ACLKX_IN                                                                           | CLK_STATE_READY     | 0               |
|   157     |    58    | DEV_BOARD0_MCASP1_ACLKX_OUT                                                                          | CLK_STATE_READY     | 0               |
|   157     |    59    | DEV_BOARD0_MCASP1_AFSR_IN                                                                            | CLK_STATE_READY     | 0               |
|   157     |    60    | DEV_BOARD0_MCASP1_AFSX_IN                                                                            | CLK_STATE_READY     | 0               |
|   157     |    61    | DEV_BOARD0_MCASP2_ACLKR_IN                                                                           | CLK_STATE_READY     | 0               |
|   157     |    62    | DEV_BOARD0_MCASP2_ACLKR_OUT                                                                          | CLK_STATE_READY     | 0               |
|   157     |    63    | DEV_BOARD0_MCASP2_ACLKX_IN                                                                           | CLK_STATE_READY     | 0               |
|   157     |    64    | DEV_BOARD0_MCASP2_ACLKX_OUT                                                                          | CLK_STATE_READY     | 0               |
|   157     |    65    | DEV_BOARD0_MCASP2_AFSR_IN                                                                            | CLK_STATE_READY     | 0               |
|   157     |    66    | DEV_BOARD0_MCASP2_AFSX_IN                                                                            | CLK_STATE_READY     | 0               |
|   157     |    67    | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                                                       | CLK_STATE_READY     | 0               |
|   157     |    68    | DEV_BOARD0_MCU_I2C0_SCL_IN                                                                           | CLK_STATE_READY     | 0               |
|   157     |    69    | DEV_BOARD0_MCU_I2C0_SCL_OUT                                                                          | CLK_STATE_READY     | 0               |
|   157     |    70    | DEV_BOARD0_MCU_OBSCLK0_IN                                                                            | CLK_STATE_READY     | 12500000        |
|   157     |    71    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                                                 | CLK_STATE_READY     | 12500000        |
|   157     |    72    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                             | CLK_STATE_READY     | 25000000        |
|   157     |    73    | DEV_BOARD0_MCU_SPI0_CLK_IN                                                                           | CLK_STATE_READY     | 0               |
|   157     |    75    | DEV_BOARD0_MCU_SPI1_CLK_IN                                                                           | CLK_STATE_READY     | 0               |
|   157     |    77    | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                                                         | CLK_STATE_READY     | 100000000       |
|   157     |    78    | DEV_BOARD0_MCU_TIMER_IO0_IN                                                                          | CLK_STATE_READY     | 0               |
|   157     |    79    | DEV_BOARD0_MCU_TIMER_IO1_IN                                                                          | CLK_STATE_READY     | 0               |
|   157     |    80    | DEV_BOARD0_MCU_TIMER_IO2_IN                                                                          | CLK_STATE_READY     | 0               |
|   157     |    81    | DEV_BOARD0_MCU_TIMER_IO3_IN                                                                          | CLK_STATE_READY     | 0               |
|   157     |    82    | DEV_BOARD0_MDIO0_MDC_IN                                                                              | CLK_STATE_READY     | 0               |
|   157     |    83    | DEV_BOARD0_MMC0_CLKLB_IN                                                                             | CLK_STATE_READY     | 0               |
|   157     |    84    | DEV_BOARD0_MMC0_CLKLB_OUT                                                                            | CLK_STATE_READY     | 0               |
|   157     |    86    | DEV_BOARD0_MMC0_CLK_OUT                                                                              | CLK_STATE_READY     | 0               |
|   157     |    87    | DEV_BOARD0_MMC1_CLKLB_IN                                                                             | CLK_STATE_READY     | 0               |
|   157     |    88    | DEV_BOARD0_MMC1_CLKLB_OUT                                                                            | CLK_STATE_READY     | 0               |
|   157     |    89    | DEV_BOARD0_MMC1_CLK_IN                                                                               | CLK_STATE_READY     | 0               |
|   157     |    90    | DEV_BOARD0_MMC1_CLK_OUT                                                                              | CLK_STATE_READY     | 0               |
|   157     |    91    | DEV_BOARD0_MMC2_CLKLB_IN                                                                             | CLK_STATE_READY     | 0               |
|   157     |    92    | DEV_BOARD0_MMC2_CLKLB_OUT                                                                            | CLK_STATE_READY     | 0               |
|   157     |    93    | DEV_BOARD0_MMC2_CLK_IN                                                                               | CLK_STATE_READY     | 0               |
|   157     |    94    | DEV_BOARD0_MMC2_CLK_OUT                                                                              | CLK_STATE_READY     | 0               |
|   157     |    95    | DEV_BOARD0_OBSCLK0_IN                                                                                | CLK_STATE_READY     | 500000000       |
|   157     |    96    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK                                       | CLK_STATE_READY     | 500000000       |
|   157     |    97    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK                                       | CLK_STATE_READY     | 192000000       |
|   157     |    98    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK                                       | CLK_STATE_READY     | 333333333       |
|   157     |    99    | DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK | CLK_STATE_READY     | 0               |
|   157     |   100    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 400000000       |
|   157     |   101    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT                                                  | CLK_STATE_READY     | 12500000        |
|   157     |   102    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8                             | CLK_STATE_READY     | 30637           |
|   157     |   103    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0                                  | CLK_STATE_READY     | 500000000       |
|   157     |   104    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                                 | CLK_STATE_READY     | 25000000        |
|   157     |   105    | DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK0_MUX_SEL_DIV_CLKOUT                                         | CLK_STATE_READY     | 32552           |
|   157     |   106    | DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0                                            | CLK_STATE_READY     | 0               |
|   157     |   107    | DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1                                            | CLK_STATE_READY     | 0               |
|   157     |   108    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK                                        | CLK_STATE_READY     | 400000000       |
|   157     |   109    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_15_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 400000000       |
|   157     |   110    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 1190000000      |
|   157     |   111    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK                                      | CLK_STATE_READY     | 170000000       |
|   157     |   112    | DEV_BOARD0_OBSCLK0_IN_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK                            | CLK_STATE_READY     | 500000000       |
|   157     |   113    | DEV_BOARD0_OBSCLK0_IN_PARENT_CLK_32K_RC_SEL_OUT0                                                     | CLK_STATE_READY     | 32768           |
|   157     |   128    | DEV_BOARD0_OSPI0_DQS_OUT                                                                             | CLK_STATE_READY     | 0               |
|   157     |   129    | DEV_BOARD0_OSPI0_LBCLKO_IN                                                                           | CLK_STATE_READY     | 0               |
|   157     |   130    | DEV_BOARD0_OSPI0_LBCLKO_OUT                                                                          | CLK_STATE_READY     | 0               |
|   157     |   131    | DEV_BOARD0_RGMII1_RXC_OUT                                                                            | CLK_STATE_READY     | 0               |
|   157     |   132    | DEV_BOARD0_RGMII1_TXC_IN                                                                             | CLK_STATE_READY     | 0               |
|   157     |   133    | DEV_BOARD0_RGMII1_TXC_OUT                                                                            | CLK_STATE_READY     | 0               |
|   157     |   134    | DEV_BOARD0_RGMII2_RXC_OUT                                                                            | CLK_STATE_READY     | 0               |
|   157     |   135    | DEV_BOARD0_RGMII2_TXC_IN                                                                             | CLK_STATE_READY     | 0               |
|   157     |   136    | DEV_BOARD0_RGMII2_TXC_OUT                                                                            | CLK_STATE_READY     | 0               |
|   157     |   137    | DEV_BOARD0_RMII1_REF_CLK_OUT                                                                         | CLK_STATE_READY     | 0               |
|   157     |   138    | DEV_BOARD0_RMII2_REF_CLK_OUT                                                                         | CLK_STATE_READY     | 0               |
|   157     |   139    | DEV_BOARD0_SPI0_CLK_IN                                                                               | CLK_STATE_READY     | 0               |
|   157     |   141    | DEV_BOARD0_SPI1_CLK_IN                                                                               | CLK_STATE_READY     | 0               |
|   157     |   143    | DEV_BOARD0_SPI2_CLK_IN                                                                               | CLK_STATE_READY     | 0               |
|   157     |   145    | DEV_BOARD0_SYSCLKOUT0_IN                                                                             | CLK_STATE_READY     | 125000000       |
|   157     |   146    | DEV_BOARD0_TCK_OUT                                                                                   | CLK_STATE_READY     | 0               |
|   157     |   147    | DEV_BOARD0_TIMER_IO0_IN                                                                              | CLK_STATE_READY     | 0               |
|   157     |   148    | DEV_BOARD0_TIMER_IO1_IN                                                                              | CLK_STATE_READY     | 0               |
|   157     |   149    | DEV_BOARD0_TIMER_IO2_IN                                                                              | CLK_STATE_READY     | 0               |
|   157     |   150    | DEV_BOARD0_TIMER_IO3_IN                                                                              | CLK_STATE_READY     | 0               |
|   157     |   151    | DEV_BOARD0_TIMER_IO4_IN                                                                              | CLK_STATE_READY     | 0               |
|   157     |   152    | DEV_BOARD0_TIMER_IO5_IN                                                                              | CLK_STATE_READY     | 0               |
|   157     |   153    | DEV_BOARD0_TIMER_IO6_IN                                                                              | CLK_STATE_READY     | 0               |
|   157     |   154    | DEV_BOARD0_TIMER_IO7_IN                                                                              | CLK_STATE_READY     | 0               |
|   157     |   155    | DEV_BOARD0_TRC_CLK_IN                                                                                | CLK_STATE_READY     | 0               |
|   157     |   156    | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT                                                                       | CLK_STATE_READY     | 0               |
|   157     |   157    | DEV_BOARD0_VOUT0_PCLK_IN                                                                             | CLK_STATE_READY     | 0               |
|   157     |   158    | DEV_BOARD0_WKUP_CLKOUT0_IN                                                                           | CLK_STATE_READY     | 25000000        |
|   157     |   159    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                            | CLK_STATE_READY     | 25000000        |
|   157     |   160    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_LFOSC0_CLKOUT                                            | CLK_STATE_READY     | 32768           |
|   157     |   161    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK                                  | CLK_STATE_READY     | 200000000       |
|   157     |   162    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK                                  | CLK_STATE_READY     | 192000000       |
|   157     |   163    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK                                 | CLK_STATE_READY     | 50000000        |
|   157     |   164    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_CLK_32K_RC_SEL_OUT0                                                | CLK_STATE_READY     | 32768           |
|   157     |   165    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT                                             | CLK_STATE_READY     | 12500000        |
|   157     |   166    | DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0                                       | CLK_STATE_READY     | 25000000        |
|---------------------------------------------------------------------------------------------------------------------------------------------------------------------|

0 Suren Porwar over 2 years ago in reply to Isee

TI__Mastermind 28995 points

Hi Isee,

Thanks for the details and dumps.

Just wanted to update you that we are internally working on having this fixed in our software. This would be fixed in our next SDK release.

Thanks,

Suren

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AM625: Configure AUDIO_EXT_REFCLK1