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TDA4AH J784s4 : Direct Memory Access (DMA) Controller(s) parallel execution

Paul D7
Prodigy 30 points


If I have understood correctly, in the TRM documentation it states that the UDMA-C can have up to 512 (UDMA-P) channels that send Transfer Requests to the DMA Controller(s) (UTC, PDMA, DRU etc ):
(i) How many of these channels can the DMA controllers process in parallel ?
(ii) How many actual DMA Controllers are there on the SOC ( ie. are the UTC, PDMA DRU physical DMA's or are the Transfer Requests multiplexed to one physical DMA ) ?

Thanks 

  • 0
    TI__Guru**** 487585 points

    Hi Paul,

    Sorry for the late reply. Many of these channels can be running in parallel, depending on the DMA controller from where they are initiating the transfer. This will taken care by the scheduler. 

    UTC, DRU, PDMA are all physically different DMA and can also be running in parallel.. For the number of instances of these DMA engines, i would request to refer to the TRM.

    Regards,

    Brijesh

  • 0
    Prodigy 30 points

    Hi Brijesh, 

    Thank you for the reply. 

    When you say DMA engines do you mean actual DMA controllers ? 

    So UTC, DRU and PDMA have their own DMA controllers ? 

    How many channels can be run in parallel for each of the DMA's . ?

    I could not find the details of the real DMA controllers in the TRM , could you please indicate where this is located as I can only find high level descriptions of UDMA-C , UDMA-P, which seems very conceptual.

    But Not how the UTC, DRU and PDMA DMA and controllers actually work.

    Is there any details like for other TI discrete DMA controllers,  where the number of channels are detailed etc. Like this - https://www.ti.com/lit/ug/slau395f/slau395f.pdf?ts=1681910738366&ref_url=https%253A%252F%252Fwww.google.co.uk%252F

    One thing that we are trying to understand, is what sort of throughput can we expect and how can we use the different DMAs to best optimise the parallel data movement that we want to achieve. 

    BR 

    Paul 

  • 0 in reply to Paul D7
    TI__Guru**** 487585 points

    Hi Paul,

    Paul D7 said:
    When you say DMA engines do you mean actual DMA controllers ? 

    Yes, engines/controllers like UTC, DRU etc..

    Paul D7 said:
    So UTC, DRU and PDMA have their own DMA controllers ? 

    Did not get it, they are the controllers. they can initiate transfer operations.

    Paul D7 said:
    How many channels can be run in parallel for each of the DMA's . ?

    Well all of them can be active, its only limited by available BW on receiving or transmitting module like DDR.

    Paul D7 said:

    I could not find the details of the real DMA controllers in the TRM , could you please indicate where this is located as I can only find high level descriptions of UDMA-C , UDMA-P, which seems very conceptual.

    But Not how the UTC, DRU and PDMA DMA and controllers actually work.

    Please refer to TRM. TRM provides details about all of these modules.

    Paul D7 said:
    One thing that we are trying to understand, is what sort of throughput can we expect and how can we use the different DMAs to best optimise the parallel data movement that we want to achieve. 

    You could refer to the datasheet to understand what kind of throughput achieved using UDMA. 

    But exactly what are you trying to achieve? UDMA is internally taken case/used by driver, so most application just needs to use driver interface. Trying to understand what's end application that you are trying to build and what's the use of different DMA components in it? 

    Regards,

    Brijesh