AM3358: How can I delete the SD-card function?

hello?

I am using am3358.

I am using the SD-card well now.

We want to remove the SD-card for other model development.

in Menuconfig

< > MMC/SD/SDIO card support ----

Remove the selection and in the DTS file

mmc1_pins_default: pinmux_mmc1_pins {
pinctrl-single,pins = <
  0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
  0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
  0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
  0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
  0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
  0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
  0x1A0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3_18 */
  0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
  >;
};

mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
pinctrl-single,pins = <
  0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7)
  0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  >;
};

and

&mmc1 {
  status = "okay";
  vmmc-supply = <&vmmc_reg>;
  bus-width = <4>;
  pinctrl-names = "default", "sleep";
  pinctrl-0 = <&mmc1_pins_default>;
  pinctrl-1 = <&mmc1_pins_sleep>;
  cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
};

I uninstalled and ran it, but the problem occurred.

==================================================================

[ 8.272493] VFS: Mounted root (ubifs filesystem) on device 0:15.
[ 8.279491] devtmpfs: mounted
[ 8.282979] Freeing unused kernel memory: 392K (c0736000 - c0798000)
[ 8.369259] Unhandled fault: external abort on non-linefetch (0x1028) at 0xf9e07134
[ 8.376965] pgd = ddcb0000
[ 8.379682] [f9e07134] *pgd=44e11452(bad)
[ 8.383728] Internal error: : 1028 [#1] PREEMPT ARM
[ 8.388627] Modules linked in:
[ 8.391705] CPU: 0 PID: 1 Comm: init Not tainted 4.1.18+ #2
[ 8.397300] Hardware name: Generic AM33XX (Flattened Device Tree)
[ 8.403417] task: dd85c000 ti: dd856000 task.ti: dd856000
[ 8.408863] PC is at omap_gpio_output+0x50/0xa0
[ 8.413412] LR is at omap_gpio_output+0x40/0xa0
[ 8.417961] pc : [<c03055b4>] lr : [<c03055a4>] psr: 20060093
[ 8.417961] sp : dd857d78 ip : 00000194 fp : dd857d94
[ 8.429487] r10: 00000000 r9 : c0375274 r8 : ddbf5bc0
[ 8.434733] r7 : ddc3e658 r6 : 0000000d r5 : a0060013 r4 : dd8d5c64
[ 8.441286] r3 : f9e07134 r2 : 00000134 r1 : 00002000 r0 : dd8d5c10
[ 8.447843] Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user
[ 8.455094] Control: 10c5387d Table: 9dcb0019 DAC: 00000015
[ 8.460863] Process init (pid: 1, stack limit = 0xdd856210)
[ 8.466456] Stack: (0xdd857d78 to 0xdd858000)
[ 8.470832] 7d60: dd8d5e9c c0305564
[ 8.479047] 7d80: ddbf5bc0 ddc3e658 dd857dac dd857d98 c030092c c0305570 ddc3e600 00000008
[ 8.487263] 7da0: dd857dbc dd857db0 c03021b8 c03008c4 dd857e0c dd857dc0 c037953c c03021a0
[ 8.495478] 7dc0: 00000000 00004d04 00000005 00001cb2 00000e0b 7f1c0300 01000415 1a131100
[ 8.503693] 7de0: 170f1200 00000016 0001c200 0001c200 ddc3e600 bec9fafc ddc9d600 ddc3e600
[ 8.511908] 7e00: dd857e5c dd857e10 c0379a1c c0379290 dd857e2c 00000500 00000005 00001cb2
[ 8.520123] 7e20: dd857e9c dd857e30 c03913d4 c057b040 170f1200 00000016 0001c200 0001c200
[ 8.528338] 7e40: bec9fafc ddc3e600 ddc9d600 ddc3e600 dd857e74 dd857e60 c0379b74 c03795fc
[ 8.536553] 7e60: e09f8000 bec9fafc dd857e9c dd857e78 c03752fc c0379b34 00005402 ddc3e600
[ 8.544768] 7e80: ddc9d600 bec9fafc ddbf5bc0 c0375274 dd857f1c dd857ea0

===================================================================================

I am attaching the dts file.

/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;

#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
model = "TI AM335x EVM";
compatible = "ti,am335x-evm", "ti,am33xx";

cpus {
cpu@0 {
cpu0-supply = <&vdd1_reg>;
};
};

memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};

vbat: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};

lis3_reg: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "lis3_reg";
regulator-boot-on;
};

backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 0>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};

panel {
compatible = "ti,tilcdc,panel";
status = "okay";

//bl-gpios = <&gpio3 21 0>; /* [FALINUX] TS 20160809 */

panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <16>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};

/* [FALINUX] TS 20160809 */
display-timings {
320x480p70 {
clock-frequency = <15000000>;
hactive = <320>;
vactive = <480>;
hfront-porch = <3>;
hback-porch = <3>;
hsync-len = <3>;
vback-porch = <2>;
vfront-porch = <2>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};

am33xx-test_module_timer {
compatible = "ti,am335x-timer";
status = "okay";
DMtimer = <&timer2>;
};
};

&am33xx_pinmux {
pinctrl-names = "default";

spi0_pins_s0: spi0_pins_s0 {
pinctrl-single,pins = <
0x150 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* spi0_sclk.spi0_sclk, INPUT_PULLUP | MODE0 */
0x154 ( PIN_OUTPUT_PULLUP | MUX_MODE0 ) /* spi0_d0.spi0_d0, INPUT_PULLUP | MODE0 */

/**************************************************************************************************************/
/* Normal GPIO Initial (Just using pruss nod) */

/* sg_gpio0_pins */
0x158 ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (B16) spi0_d1.gpio0[4] */ /*Parallel SLELCTIN_ C3*/
0x144 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (H18) rmii1_refclk.gpio0[29] */ /*Parallel S_BUSY S7*/
0x164 ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (C18) eCAP0_in_PWM0_out.gpio0[7] */ /*Parallel INIT_ C2*/
0x20 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (U10) gpmc_ad8.gpio0[22] */ /*Pause_Cancel_SW*/
0x24 ( PIN_OUTPUT_PULLDOWN| MUX_MODE7 ) /* (T10) gpmc_ad9.gpio0[23] */ /*DPI_Info_FPGA*/
0x1b4 (PIN_INPUT | MUX_MODE7 ) /* (D14) xdma_event_intr1.gpio0[20] */ /*Cutter Switch*/
0x1b0 ( PIN_INPUT | MUX_MODE7 ) /* (A15) xdma_event_intr0.gpio0[19] */ /*Peeler Switch*/
0x21c ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (F16) USB0_DRVVBUS.gpio0[18] */ /*BT_ATCMD*/
0x15C (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.gpio0_5 */ /*BT_DUT*/
0x2c ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (U12) gpmc_ad11.gpmc_ad11 gpio0[27]*/ /*BT_WL_SEL*/
0x178 (PIN_INPUT | MUX_MODE7 ) /* (D18) uart1_ctsn.gpio0[12] */ /*Serial CTS*/
0x17c (PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (D17) uart1_rtsn.gpio0[13] */ /*Serial RTS*/

/* sg_gpio1_pins */
0x60 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (V16) gpmc_a8.gpio1[24] */ /*MOT_EN*/
0x64 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (U16) gpmc_a9.gpio1[25] */ /*MOT_RST*/
0x6c ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (V17) gpmc_a11.gpio1[27] */ /*MOT_DIR*/
0x78 ( PIN_OUTPUT | MUX_MODE2 ) /* (U18) gpmc_be1n.gpio1[28] */ /*nReset_USB USB Hub Rest*/
//0x84 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (V9) gpmc_csn2.gpio1[31] */ /*GREEN_LED_CTL*/
0x84 ( PIN_OUTPUT | MUX_MODE0 ) /* (V9) gpmc_csn2.gpmc_csn2 */ /*Key Interface Chip select*/
0x80 (PIN_OUTPUT | MUX_MODE0) /* (U9) gpmc_csn1.gpio1[30] */ /*Parallel Interface CS1*/
//0x40 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (R13) gpmc_a0.gpio1[16] */ /*Parallel P_SELECT_ S4*/
0x40 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (R13) gpmc_a0.gpio1[16] */ /*Parallel P_SELECT_ S4*/
0x48 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (U14) gpmc_a2.gpio1[18] */ /*Parallel P_ACK S6*/
0x54 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (V15) gpmc_a5.gpio1[21] */ /*Parallel P_EOORO_ S5*/
0x58 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (U15) gpmc_a6.gpio1[22] */ /*Parallel FAULT_ S3*/
0x5c ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (T15) gpmc_a7.gpio1[23] */ /*Parallel PaAUTO_FD C1*/
0x68 ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (T16) gpmc_a10.gpio1[26] */ /*Parallel P_INT_ C0*/
0x168 (PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (E18) uart0_ctsn.gpio1[8] */ /*LAT*/
0x44 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (V14) gpmc_a1.gpio1[17] */ /*Cutter Enable*/
0x50 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (R14) gpmc_a4.gpio1[20] */ /*REWINDER ENABLE*/
0x4c ( PIN_INPUT | MUX_MODE7 ) /* (T14) gpmc_a3.gpio1[19] */ /*RIBBON_END*/
0x38 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (V13) gpmc_ad14.gpio1[14] */ /*BT_NRESET*/ /*WL_NRESET*/
0x3c ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (U13) gpmc_ad15.gpio1[15] */ /*BT_STATUS*/ /*WLF_NRESET*/

/* sg_gpio2_pins */
0x88 ( PIN_OUTPUT | MUX_MODE0 ) /* (T13) gpmc_csn3.gpio2[0] */ /*TP16*/
//0x8c ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (V12) gpmc_clk.gpio2[1] */ /*RED_LED_CTL*/
0x8c ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (V12) gpmc_clk.gpio2[1] */ /*FEED_SW*/

/* sg_gpio3_pins */
/*0x190 ( PIN_OUTPUT_PULLUP | MUX_MODE7 )*/ /* (A13) mcasp0_aclkx.gpio3[14] */ /*LCD_DISP*/
//0x190 ( PIN_OUTPUT | MUX_MODE1 ) /* (A13) mcasp0_aclkx.ehrpwm0A */ /*PWM*/
//0x1e4 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (C14) EMU0.gpio3[7] */ /*FEED_S_W1*/
//0x1e8 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (B14) EMU1.gpio3[8] */ /*FEED_S_W2*/
//0x10c ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (H17) gmii1_crs.gpio3[1] */ /*BT_NRESET*/
0x110 ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (J15) gmii1_rxer.gpio3[2] */ /*BT_STATUS*/
0x1e4 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (C14) EMU0.gpio3[7] */ /*LED_Ready*/
0x1e8 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (B14) EMU1.gpio3[8] */ /*LED_Error*/
0x1a8 ( PIN_INPUT | MUX_MODE7 ) /* (D13) mcasp0_axr1.gpio3[20] */ /*RIBBON_SW_1(cover switch)*/
0x198 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (D12) mcasp0_axr0.gpio3[16] */ /*TPH_VP_ON_OFF_CTL*/
0x1ac ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (A14) mcasp0_ahclkx.mcasp0_ahclkx gpio3[21] */ /*SERIAL_INS*/

0x108 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (H16) gmii1_col.gmii1_col gpio3[0]*/ /*DPI_Info_FPGA*/
0x10c ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (H17) gmii1_crs.gmii1_crs gpio3[1]*/ /*Buzzer output signal*/

/**************************************************************************************************************/

>;
};

ehrpwm0_pins_default: ehrpwm0_pins_default {
pinctrl-single,pins = <
0x190 ( PIN_OUTPUT_PULLUP | MUX_MODE1 ) /* (A13) mcasp0_aclkx.ehrpwm0A */ /*PWM*/
0x194 ( PIN_OUTPUT_PULLDOWN | MUX_MODE1 ) /* (B13) mcasp0_fsx.ehrpwm0B */
>;
};

ehrpwm0_pins_sleep: ehrpwm0_pins_sleep {
pinctrl-single,pins = <
0x190 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (A13) mcasp0_aclkx.ehrpwm0A */ /*PWM*/
0x194 ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (B13) mcasp0_fsx.ehrpwm0B */
>;
};


i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};

uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};

uart1_pins_default: pinmux_uart1_pins_default {
pinctrl-single,pins = <
0x180 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (D16) uart1_rxd.uart1_rxd */
0x184 ( PIN_OUTPUT_PULLDOWN | MUX_MODE0 ) /* (D15) uart1_txd.uart1_txd */
//0x178 ( PIN_INPUT | MUX_MODE0 ) /* (D18) uart1_ctsn.uart1_ctsn */
//0x17c ( PIN_OUTPUT_PULLDOWN | MUX_MODE0 ) /* (D17) uart1_rtsn.uart1_rtsn */
>;
};

uart1_pins_sleep: pinmux_uart1_pins_sleep {
pinctrl-single,pins = <
0x180 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (D16) uart1_rxd.uart1_rxd */
0x184 ( PIN_OUTPUT_PULLDOWN | MUX_MODE0 ) /* (D15) uart1_txd.uart1_txd */
//0x178 ( PIN_INPUT | MUX_MODE0 ) /* (D18) uart1_ctsn.uart1_ctsn */
//0x17c ( PIN_OUTPUT_PULLDOWN | MUX_MODE0 ) /* (D17) uart1_rtsn.uart1_rtsn */
>;
};


nandflash_pins_default: nandflash_pins_default {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};

nandflash_pins_sleep: nandflash_pins_sleep {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
#if 1
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
>;
};

cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
#else
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x108 ( PIN_INPUT | MUX_MODE0 ) /* (H16) gmii1_col.gmii1_col */
0x10c ( PIN_INPUT | MUX_MODE0 ) /* (H17) gmii1_crs.gmii1_crs */
0x110 ( PIN_INPUT | MUX_MODE0 ) /* (J15) gmii1_rxer.gmii1_rxer */
0x114 ( PIN_OUTPUT | MUX_MODE0 ) /* (J16) gmii1_txen.gmii1_txen */
0x118 ( PIN_INPUT | MUX_MODE0 ) /* (J17) gmii1_rxdv.gmii1_rxdv */
0x12c ( PIN_INPUT | MUX_MODE0 ) /* (K18) gmii1_txclk.gmii1_txclk */
0x130 ( PIN_INPUT | MUX_MODE0 ) /* (L18) gmii1_rxclk.gmii1_rxclk */
0x128 ( PIN_OUTPUT | MUX_MODE0 ) /* (K17) gmii1_txd0.gmii1_txd0 */
0x124 ( PIN_OUTPUT | MUX_MODE0 ) /* (K16) gmii1_txd1.gmii1_txd1 */
0x120 ( PIN_OUTPUT | MUX_MODE0 ) /* (K15) gmii1_txd2.gmii1_txd2 */
0x11c ( PIN_OUTPUT | MUX_MODE0 ) /* (J18) gmii1_txd3.gmii1_txd3 */
0x140 ( PIN_INPUT | MUX_MODE0 ) /* (M16) gmii1_rxd0.gmii1_rxd0 */
0x13c ( PIN_INPUT | MUX_MODE0 ) /* (L15) gmii1_rxd1.gmii1_rxd1 */
0x138 ( PIN_INPUT | MUX_MODE0 ) /* (L16) gmii1_rxd2.gmii1_rxd2 */
0x134 ( PIN_INPUT | MUX_MODE0 ) /* (L17) gmii1_rxd3.gmii1_rxd3 */
>;
};

cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x108 ( PIN_INPUT_PULLDOWN | MUX_MODE7) /* (H16) gmii1_col.gmii1_col */
0x10c ( PIN_INPUT_PULLDOWN | MUX_MODE7) /* (H17) gmii1_crs.gmii1_crs */
0x110 ( PIN_INPUT_PULLDOWN | MUX_MODE7) /* (J15) gmii1_rxer.gmii1_rxer */
0x114 ( PIN_INPUT_PULLDOWN | MUX_MODE7) /* (J16) gmii1_txen.gmii1_txen */
0x118 ( PIN_INPUT_PULLDOWN | MUX_MODE7) /* (J17) gmii1_rxdv.gmii1_rxdv */
0x12c ( PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K18) gmii1_txclk.gmii1_txclk */
0x130 ( PIN_INPUT_PULLDOWN | MUX_MODE7) /* (L18) gmii1_rxclk.gmii1_rxclk */
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (K17) gmii1_txd0.gmii1_txd0 */
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K16) gmii1_txd1.gmii1_txd1 */
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (K15) gmii1_txd2.gmii1_txd2 */
0x11c ( PIN_INPUT_PULLDOWN | MUX_MODE7) /* (J18) gmii1_txd3.gmii1_txd3 */
0x140 ( PIN_INPUT_PULLDOWN | MUX_MODE7) /* (M16) gmii1_rxd0.gmii1_rxd0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (L15) gmii1_rxd1.gmii1_rxd1 */
0x138 ( PIN_INPUT_PULLDOWN | MUX_MODE7) /* (L16) gmii1_rxd2.gmii1_rxd2 */
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (L17) gmii1_rxd3.gmii1_rxd3 */
>;
};
#endif
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};

davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};

#if 0

mmc1_pins_default: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x1A0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3_18 */
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};

mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
pinctrl-single,pins = <
0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
#endif

lcd_pins_default: lcd_pins_default {
pinctrl-single,pins = <
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
/*0x1ac(PIN_OUTPUT_PULLUP | MUX_MODE7)*/ /* gpmc_ad10.gpio3_21 LCD_POWER_EN */
0x28 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_ad10.gpio0_26 LCD_RESET */
>;
};

lcd_pins_sleep: lcd_pins_sleep {
pinctrl-single,pins = <
0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */
0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */
0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */
0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */
0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */
0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */
0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */
0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */
0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */
0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */
0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */
0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */
0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */
0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */
0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */
0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */
0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */
0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */
0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */
/*0x1ac(PIN_OUTPUT_PULLUP | MUX_MODE7)*/ /* gpmc_ad10.gpio3_21 */
0x28 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_ad10.gpio0_26 */
>;
};

pruss_pins: pruss_pins {
pinctrl-single,pins = <
//0x19c ( PIN_OUTPUT_PULLUP | MUX_MODE5 ) /* (C12) mcasp0_ahclkr.pr1_pru0_pru_r30[3] */
0x1a4 ( PIN_OUTPUT_PULLDOWN | MUX_MODE5 ) /* (C13) mcasp0_fsr.pr1_pru0_pru_r30[5], Motor, Default : L */
0x30 ( PIN_OUTPUT_PULLUP | MUX_MODE6 ) /* (T12) gpmc_ad12.pr1_pru0_pru_r30[14], Strobe, Default : H */
0x34 ( PIN_OUTPUT_PULLUP | MUX_MODE6 ) /* (R12) gpmc_ad13.pr1_pru0_pru_r30[15], Latch, Default : H */
>;
};

};

&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_s0>;
ti,pindir-d0-out-d1-in = <1>;
spidev@0 {
spi-max-frequency = <24000000>; //24MHz
//spi-max-frequency = <10000000>; //12MHz
//spi-max-frequency = <2400000>; //2.5MHz
reg = <0>;
compatible = "linux,spidev";
};
};

&pruss {
pinctrl-names = "default";
pinctrl-0 = <&pruss_pins>;
status = "okay";
};

&timer2 {
status = "okay";
};

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;

status = "okay";
};

&uart1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pins_default>;
pinctrl-1 = <&uart1_pins_sleep>;

status = "okay";
};

&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;

status = "okay";
clock-frequency = <400000>;

tps: tps@2d {
reg = <0x2d>;
};
};

&usb {
status = "okay";
};

&usb_ctrl_mod {
status = "okay";
};

&usb0_phy {
status = "okay";
};

&usb1_phy {
status = "okay";
};

&usb0 {
status = "okay";
};

&usb1 {
status = "okay";
dr_mode = "host";
};

&cppi41dma {
status = "okay";
};

&lcdc {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_pins_default>;
pinctrl-1 = <&lcd_pins_sleep>;
};

&elm {
status = "okay";
};

&gpmc {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nandflash_pins_default>;
pinctrl-1 = <&nandflash_pins_sleep>;
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&intc>;
interrupts = <100>;
ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
/*ti,nand-ecc-opt = "bch8";*/ /* NAND : 256MB spere : 64*/
ti,nand-ecc-opt = "bch16"; /* NAND : 512MB spere : 128*/
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
#if 0
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000C0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001C0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001E0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00A00000 0x0D000000>;
};
partition@10 {
label = "NAND.UserArea";
reg = <0x0DA00000 0x00200000>;
};
partition@11 {
label = "NAND.PritnerSetting";
reg = <0x0DC00000 0x00100000>;
};
partition@12 {
label = "NAND.RawPartition1";
reg = <0x0DD00000 0x00100000>;
};
partition@13 {
label = "NAND.default-elements";
reg = <0x0DE00000 0x02200000>;
};

#===============================
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00020000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000A0000 0x00080000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x00120000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x00140000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00160000 0x00400000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00560000 0x05000000>;
};
partition@10 {
label = "NAND.UserArea";
reg = <0x05560000 0x00200000>;
};
partition@11 {
label = "NAND.PritnerSetting";
reg = <0x05760000 0x00100000>;
};
partition@12 {
label = "NAND.RawPartition1";
reg = <0x05860000 0x00100000>;
};
partition@13 {
label = "NAND.default-elements";
reg = <0x05960000 0x02200000>;
};

#===============================

partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.u-boot-spl-os";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.u-boot";
reg = <0x00040000 0x00080000>;
};
partition@3 {
label = "NAND.kernel";
reg = <0x000C0000 0x00500000>;
};
partition@4 {
label = "NAND.UserArea";
reg = <0x005C0000 0x00300000>;
};
partition@5 {
label = "NAND.PritnerSetting";
reg = <0x008C0000 0x00100000>;
};
partition@6 {
label = "NAND.RawPartition1";
reg = <0x009C0000 0x00100000>;
};
partition@7{
label = "NAND.file-system";
reg = <0x00AC0000 0x07000000>;
};
partition@8 {
label = "NAND.file-system-1";
reg = <0x07AC0000 0x07000000>;
};
partition@9 {
label = "NAND.default-elements";
reg = <0x0EAC0000 0x04000000>; //total : 320M , free: 190M
};

#===============================
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.u-boot-spl-os";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.u-boot";
reg = <0x00040000 0x00080000>;
};
partition@3 {
label = "NAND.kernel";
reg = <0x000C0000 0x00500000>;
};
partition@4 {
label = "NAND.UserArea";
reg = <0x005C0000 0x04000000>;
};
partition@5 {
label = "NAND.PritnerSetting";
reg = <0x045C0000 0x00100000>;
};
partition@6 {
label = "NAND.RawPartition1";
reg = <0x046C0000 0x00100000>;
};
partition@7{
label = "NAND.file-system";
reg = <0x047C0000 0x07000000>;
};
partition@8 {
label = "NAND.file-system-1";
reg = <0x0b7C0000 0x07000000>;
};
partition@9 {
label = "NAND.default-elements";
reg = <0x127C0000 0x04000000>; //total : 380M , free: 132M
};

#else
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.u-boot-spl-os";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.u-boot";
reg = <0x00040000 0x00080000>;
};
partition@3 {
label = "NAND.kernel";
reg = <0x000C0000 0x00500000>;
};
partition@4 {
label = "NAND.UserArea";
reg = <0x005C0000 0x02800000>;
};
partition@5 {
label = "NAND.PritnerSetting";
reg = <0x02DC0000 0x00100000>;
};
partition@6 {
label = "NAND.RawPartition1";
reg = <0x02EC0000 0x00100000>;
};
partition@7{
label = "NAND.file-system";
reg = <0x02FC0000 0x07000000>;
};
partition@8 {
label = "NAND.file-system-1";
reg = <0x09FC0000 0x07000000>;
};
partition@9 {
label = "NAND.default-elements";
reg = <0x10FC0000 0x04000000>; //total : 350M , free: 162M
};
partition@10 {
label = "NAND.default-elements1";
reg = <0x14FC0000 0x04000000>;
};
partition@11 {
label = "NAND.reserve";
reg = <0x18FC0000 0x00100000>;
};
#endif
};
};

#include "tps65910.dtsi"

&tps {
vcc1-supply = <&vbat>;
vcc2-supply = <&vbat>;
vcc3-supply = <&vbat>;
vcc4-supply = <&vbat>;
vcc5-supply = <&vbat>;
vcc6-supply = <&vbat>;
vcc7-supply = <&vbat>;
vccio-supply = <&vbat>;

regulators {
vrtc_reg: regulator@0 {
regulator-always-on;
};

vio_reg: regulator@1 {
regulator-always-on;
};

vdd1_reg: regulator@2 {
/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1378000>;
regulator-boot-on;
regulator-always-on;
};

vdd2_reg: regulator@3 {
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};

vdd3_reg: regulator@4 {
regulator-always-on;
};

vdig1_reg: regulator@5 {
regulator-always-on;
};

vdig2_reg: regulator@6 {
regulator-always-on;
};

vpll_reg: regulator@7 {
regulator-always-on;
};

vdac_reg: regulator@8 {
regulator-always-on;
};

vaux1_reg: regulator@9 {
regulator-always-on;
};

vaux2_reg: regulator@10 {
regulator-always-on;
};

vaux33_reg: regulator@11 {
regulator-always-on;
};

vmmc_reg: regulator@12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};

&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};

&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
#if 1
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
};

&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii-txid";
};

#else

&cpsw_emac0 {
phy_id = <&davinci_mdio>, <31>;
//phy-mode = "rgmii-txid";
phy-mode = "mii";
//phy-mode = "gmii-txid";
};

&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
//phy-mode = "rgmii-txid";
phy-mode = "mii";
//phy-mode = "gmii-txid";
};
#endif

#if 0
&tscadc {
status = "okay";
tsc {
ti,wires = <4>;
ti,x-plate-resistance = <200>;
ti,coordinate-readouts = <5>;
ti,wire-config = <0x00 0x11 0x22 0x33>;
ti,charge-delay = <0x400>;
};

adc {
ti,adc-channels = <0 1 2 3>;
io-channels = <&am335x_adc 0>, <&am335x_adc 1>, <&am335x_adc 2>, <&am335x_adc 3>;
io-channel-names = "AIN0", "AIN1", "AIN2", "AIN3";
};
};
#else
&tscadc {
status = "okay";
clocks = <&adc_tsc_fck>;

adc {
ti,adc-channels = <0 1 2 3>;
io-channels = <&am335x_adc 0>, <&am335x_adc 1>, <&am335x_adc 2>, <&am335x_adc 3>;
io-channel-names = "AIN0", "AIN1", "AIN2", "AIN3";
};
};
#endif

&epwmss0 {
status = "okay";
ehrpwm0: ehrpwm@48300200 {
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm0_pins_default>;
pinctrl-1 = <&ehrpwm0_pins_sleep>;
status = "okay";
};
};

#if 0

&mmc1 {
status = "okay";
vmmc-supply = <&vmmc_reg>;
bus-width = <4>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_sleep>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
};

#endif

How can I solve the above problem?