C6726B dMAX FIFO mode

Dear TI Support,

It is now July 21st.  I first submitted these questions on July 11th.  I have not received a reply yet.

Can you please look into these issues, and get me the answers?

Thanks,

Steve Tuttle

Steve.

In the past two weeks while you have been waiting for a response, have you tried coding up these scenarios and trying to evaluate the performance? What results have you found, if so?

It is not clear to me how anyone will be able to answer your questions without building these scenarios and trying them. I do not have the facilities for that, and it would appear that no one else has been able to do it, either. Perhaps some added experience from your work over the past two weeks will gather some feedback based on your observations.

Regards,
RandyP

Randy,

While there is some information I can gain by experimentation, I cannot answer the most fundamental question without help from TI support:

Can the Hi priority dMAX unit and the Lo priority dMAX unit share the same FIFO descriptor without corrupting the descriptor's data?

Note that both of these dMAX units run asynchronously, and both units will be updating the FIFO descriptor's contents.  Are you telling me that no one at TI can answer that question for me?

Steve

Randy,

In those 2 weeks, I have built a system that uses dMAX to transfer 2 8-slot TDM streams from McASP into external SDRAM.

I used the CPU to copy data from the FIFO (in SDRAM) to buffers in internal RAM.  This is not an ideal solution, since I would rather have the CPU doing other processing during that 'copy' time.  The CPU manually updates the 'read pointer' in the FIFO descriptor after a block of samples has been read from the FIFO.

This seems to be working well, but I would rather have the dMAX unit copying the data from the FIFO into the internal RAM buffers.

The problem is, if I need to use the hi priority dMAX unit for reading the FIFO, I am going to miss McASP DMA events.  It takes 274 dMAX clocks for the hi priority dMAX unit to service the 2 serializers I am using in McASP, which equates to 2.192uS, given the dMAX clock is running at 125MHz.  TDM/McASP dma events arrive every 2.604uS.  If that hi priority dMAX unit has to compete for bandwidth with a hi priority dMAX transfer from SDRAM (the FIFO read) to internal RAM buffers, then the latency problems will cause some of the McASP dma request events to be lost.

However, the lo priority dMAX unit can run concurrently with the hi priority unit, and they should only conflict with each other when contending for simultaneous access to the SDRAM resource (the FIFO).  So I could use the hi priority dMAX unit to write data into the FIFO (from McASP), and use the lo priority dMAX unit to read the FIFO and copy data into the internal RAM buffers.

The catch here is that both the lo priority and hi priority units need to share the same FIFO descriptor.  Both dMAX units will need to update the status flags in the FIFO descriptor.

How does the dMAX unit update the flags in the descriptor?  Is it some form of read-modify-write operation?  If so, then is there a chance that the hi priority dMAX unit will modify the flags in the FIFO descriptor, while the lo priority unit is in the middle of its own read-modify-write sequence?  Or are these writes to the flags in the descriptor indivisible?

Steve

Still waiting for your reply.

Randy,

Thanks for sending me a reply.  Forgive my impatience - but I have been waiting over 2 weeks.  It is OK in an academic setting to wait for 'some other expert' to make a contribution to a discussion.  But I am in a business setting, and I have a schedule to meet.  This is not an academic exercise for me.

The FIFO mode of dMAX offers me advantages over a ping-pong buffer scheme.  I can see how one could 'sort of' simulate the larger set of buffers the FIFO mode offers, by using a large ping buffer and a large pong buffer, and using dMAX to transfer a subset of that data to internal memory for processing, as you have suggested.

The FIFO method does work better for us, in our application.

Since you are not familiar with the FIFO mode details, please put me in touch with a TI employee that has the information I need.  The answer to my questions should be readily available to the engineer(s) that designed the dMAX subsystem.

Steve