AM4378: ADC output does not change

Hello deguchi-hideaki

Thank you for the query.

Based on your inputs i understand that the ADC functional normally and see the behavior when ESD is applied.

This is a system level issue and could you confirm the required ESD protections are provided at the input of the ADC.

Regards,

Sreenivasa

Hello Kallikuppa Sreenivasa

Thank you for your reply.
The input voltage value is 0V to 1.7V.
VDDS_ADC0 is inputting LDO output: 1.8V.

CR low-pass filter (1kΩ + 1000pF) and diode clamp are available as ESD countermeasures.

Regards,

Deguchi

Hello deguchi-hideaki

Thank you for the input.

Would you be able to share the schematics for a quick review.

Please check the ADC clock source - crystal or oscillator, termination of any ADC input that is not used and the diode used - ESD or overvoltage protection type used.

Regards,

Sreenivasa

Hello Kallikuppa Sreenivasa

Thank you for your reply.
Sorry, I can't disclose the circuit diagram.
The clock uses 24MHz.
A PIN diode is used as an ESD countermeasure.

The phenomenon is similar to the contents of the following URL.

community.silabs.com/.../f330-adc-latchup

If the ADC built into the AM4378 latches up, will the output be locked regardless of the input voltage level?

Regards,

Deguchi

Hello deguchi-hideaki

Thank you for the note and understand.

We have observed ADC related issues caused due to ADC FSM_BUSY

I added additional details in the below message.

Regards,

Sreenivasa

Hello Kallikuppa Sreenivasa

Thank you for your reply.

I can't see the link

I added the details below as the link may be internal..

Regards,

Deguchi

Hello deguchi-hideaki

Please refer below inputs from the experts.

The only time we have seen the ADC lockup like they describe was when it was exposed to some external noise source that caused the FSM to deviate from its normal operation.  They need to find the noise source and eliminate it.

 I have a suggestion.  The ADC receives its clock directly from the HF oscillator, where most other peripherals receive their clock from one of the internal PLLs.  I have seen at least one case where noise coupled on the slow changing HF oscillator input signal that comes from the crystal circuit, and the noise produced a non-monotonic transition on the signal as it crossed the input buffer switching threshold.  If this happens, the HF oscillator may create a short clock cycle (glitch) on its output.  The glitch is filtered by the internal PLL, so most peripherals are not affected by it.  The glitch can over-clock the ADC FSM and cause it to perform unpredictable operations or lockup.

 I suggest they perform a temporary modification to the unit experiencing the issue by replacing the crystal circuit with a 1.8V LVCMOS clock source that is able to source the HF oscillator with fast rise/fall time.  The fast rise/fall time makes it difficult for noise to produce a non-monotonic transition on the reference clock signal.  I suggest the select a clock source that is able to provide a rise/fall time that is less than 5ns at the HF oscillator input.  This may confirm the source of the problem if the lockup issue is resolved.

 Note: In many cases electrical noise is unique to a specific implementation.  Therefore, this test needs to be performed on the same system that is constituently experiencing the problem while operating in the same environment.  For example, do not move the system to a different place when running this test.  It is import to only change one thing at a time.  They do not want to be fooled by moving it to another location that doesn’t exposed the system to the same noise sources.

Regards,

Sreenivasa

Hello deguchi-hideaki

The summary is you will have to make the ADC section including clocking, power and the inputs robust against ADC  by adding  additional protection or perform some additional analysis to verify if there are any weakness in the design that could cause the ADC to see unexpected transients.

Regards,

Sreenivasa

Hello Kallikuppa Sreenivasa

Thank you for your reply.

Verify with 1.8V LVCMOS.
I need some time, but I will contact you again.

Regards,

Deguchi

Hello deguchi-hideaki

Thank you for the inputs.

Please check if there is any additional improvement that can be done around the ADC input, supply and clock.

We have observed improvement is customer systems when these functional blocks were taken reviewed and made improvements.

if you think you can have the test results in a week, we can have the same thread waiting for inputs.

if you believe this will take 3-4 weeks, we can close the thread and start a new thread referencing this thread.

Regards,

Sreenivasa