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DRA821U: How do I create an application image for the DRA821?

Masaki Soga
Prodigy 70 points
Part Number: DRA821U
Other Parts Discussed in Thread: DRA821,

I am working in a Windows environment.

I made an application image using out2rprc and MulticoreImageGen from an application created with CCS.
I wrote it as an app file to the SD card in MMCSD boot mode and started it, but an error occurred during deployment.
The error is below.

> Sciclient_procBootSetProcessorCfg, ProcId 0x6, EntryPoint 0x54...
> Sciclient_procBootSetProcessorCfg...FAILED

Below are the steps that worked:
1. out → rprc conversion with out2rprc (for the number of cores)
2. Image creation with MulticoreImageGen

> MulticoreImageGen LE 55 appImageName 0 A72_0.rprc 10 R5F_0.rprc 8 sciserver_testapp_freertos_mcu1_0_release.rprc

Are there any problems so far?

Do you recognize the core number of DRA821 as below?

Main A72-0 0
Main A72-1 1
Main R5F-0 10
Main R5F-1 11
MCU R5F-0 8
MCU R5F-0 9

Where can I find a document that shows the core number of the DRA821?

  • 0 in reply to Parth Nagpal
    Prodigy 70 points

    Hi, Parth

    Parth Nagpal said:
    Please refer to the documentation https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_02_00_05/exports/docs/pdk_jacinto_08_02_00_21/docs/userguide/jacinto/boot/boot_k3.html?highlight=multicoreimagegen#compiling-appimage-that-can-be-loaded-by-sbl for details.

    Is this URL correct as a documentation link for DRA821U?
    Isn't the URL below?
    software-dl.ti.com/.../boot_k3.html loadable with sbl

    I have confirmed the above documents.
    Converted to rprc according to documentation, created appimage with MulticoreImageGen, successfully loaded Main A72-0 from SBL.
    I converted Main R5-0 in the same way and incorporated it with MulticoreImageGen, but an error occurred.
    The memory map does not overlap with SBL, SYSFW.
    Are there any other limitations when using MulticoreImageGen to create an appimage?

    As I asked earlier, could you please provide me with a document that shows the core ID of the DRA821?
    It's not clear in the documentation below which ID corresponds to which domain core.
    > The values used for the Core ID and Device ID can be found in sbl/soc/k3/ sbl_slave_core_boot.h

    thank you.

  • 0 in reply to Masaki Soga
    TI__Mastermind 42135 points

    Hi,

    Masaki Soga said:
    The values used for the Core ID and Device ID can be found in sbl/soc/k3/ sbl_slave_core_boot.h

    This is correct, you need to use the same core ids. If you still have doubts, you can build any application using the PDK build procedures and check the logs to see if you are using the correct ID.

    Masaki Soga said:
    I converted Main R5-0 in the same way and incorporated it with MulticoreImageGen, but an error occurred.

    Can you please share the MultiCoreImageGen command that you are running?
    And what errors are you seeing while running the application on Main R5 core? Can you please share the logs?

    Also, why are you not using the PDKs build procedure? Are you seeing any issues with that?

    Regards,
    Parth

  • 0 in reply to Parth Nagpal
    Prodigy 70 points

    Hi

    Parth Nagpal said:
    This is correct, you need to use the same core ids. If you still have doubts, you can build any application using the PDK build procedures and check the logs to see if you are using the correct ID.

    sbl_slave_core_boot.h contains the following information:

    #define MPU1_CPU0_ID                    (0U)
#define MPU1_CPU1_ID                    (1U)
#define MPU1_CPU2_ID                    (2U)
#define MPU1_CPU3_ID                    (3U)
#define MPU2_CPU0_ID                    (4U)
#define MPU2_CPU1_ID                    (5U)
#define MPU2_CPU2_ID                    (6U)
#define MPU2_CPU3_ID                    (7U)
#define MCU1_CPU0_ID                    (8U)
#define MCU1_CPU1_ID                    (9U)
#define MCU2_CPU0_ID                    (10U)
#define MCU2_CPU1_ID                    (11U)
#define MCU3_CPU0_ID                    (12U)
#define MCU3_CPU1_ID                    (13U)
#define MCU4_CPU0_ID                    (14U)
#define MCU4_CPU1_ID                    (15U)

    With this information, it is not possible to determine which identity the A-core of the main domain is.
    Please let me know the document that can confirm the ID of each core of DRA821U.

    Parth Nagpal said:
    Can you please share the MultiCoreImageGen command that you are running?


    As I mentioned earlier, here it is:
    > MulticoreImageGen LE 55 appImageName 0 A72_0.rprc 10 R5F_0.rprc 8 sciserver_testapp_freertos_mcu1_0_release.rprc

    Parth Nagpal said:
    And what errors are you seeing while running the application on Main R5 core? Can you please share the logs?

    The error is as written above.
    > Sciclient_procBootSetProcessorCfg, ProcId 0x6, EntryPoint 0x54...
    > Sciclient_procBootSetProcessorCfg...FAILED

    Parth Nagpal said:
    Also, why are you not using the PDKs build procedure? Are you seeing any issues with that?
    Does this mean that the user application should be included in the PDK build?

    https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j7200/08_04_00_04/exports/docs/pdk_j7200_08_04_00_19/docs/userguide/j7200/boot/boot_k3.html#compiling-appimage-that-can-be-loaded-by-sbl

    The image is created according to the Multicore Images of the above URL.

    User applications are developed with CCS.
    The OUT file output by CCS is converted to rprc and an image is created with MulticoreImageGen.

    Am I doing something wrong?

  • 0 in reply to Masaki Soga
    TI__Mastermind 42135 points

    Hi,

    I would recommend you to use the PDK build environment. This will be much easier for you.

    You can either modify the existing example or you can add a new example for your requirements. Please see the documentation for details

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1120181/faq-tda4vm-how-to-build-custom-examples-in-pdk

    Regards,
    Parth

  • 0 in reply to Parth Nagpal
    Prodigy 70 points

    Hi

    I checked the URL.
    The presented demo sample creation method looks like MCU1_0 single core.
    For multicore, I think you'll need core allocation as you're asking above.
    However, I do not know which A72-1 core in the MAIN domain of DRA821 corresponds to the notation such as MCU1_0.
    I would like a document that clearly describes the response.

  • 0 in reply to Masaki Soga
    TI__Guru 53413 points

    Hi Soga-san,

    I found in the documentation the following: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j7200/08_04_00_04/exports/docs/pdk_j7200_08_04_00_19/docs/userguide/j7200/modules/ipc.html?highlight=mpu1_0#available-core-names

    To quote from there:

    J7200:
    • mpu1_0 (A72)
    • mcu1_0 (mcu-r5f0_0)
    • mcu1_1 (mcu-r5f0_1)
    • mcu2_0 (main-r5f0_0)
    • mcu2_1 (main-r5f0_1)

    Let me know if this answers your question and if clarifications need to be made.

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Prodigy 70 points

    Hi Fujiwara-san

    thank you for answering.

    Core ID resolved.

    The original problem has not been resolved.
    Failed to load application image.

    As I wrote at the beginning, I created an application image with MulticoreImageGen, but an error occurs when loading


    Sciclient_procBootSetProcessorCfg, ProcId 0x6, EntryPoint 0x54...
Sciclient_procBootSetProcessorCfg... failed

    I would like to know how to solve this problem.

     Regards,

    Masaki

  • 0 in reply to Masaki Soga
    TI__Mastermind 42135 points

    Hi Masaki-san,

    Can you please share the .out generated at your end and and detailed steps you are using to convert the .out to appimage?

    Regards,
    Parth

  • 0 in reply to Parth Nagpal
    Prodigy 70 points

    Hi Parth,

    I am currently creating a project in CCS and creating an application.

    The procedure for creating an application image is as follows.

    1. Build with CCS
    2. Convert the output out file with the out2rprc command
      out2rprc.exe main_a72_core0.out main_a72_core0.rprc
      out2rprc.exe main_r5f_core0.out main_r5f_core0.rprc
    3. Create application image
      MulticoreImageGen LE 55 appImage 0 main_a72_core0.rprc 4 main_r5f_core0.rprc 8 sciserver_testapp_freertos_mcu1_0_release.rprc

    Sorry, the .out files contain copyrighted code and cannot be shared.
    Attached is the SBL startup log at the time of failure.

    SBL Revision: 01.00.10.01 (Apr 10 2023 - 11:13:05)
TIFS  ver: 8.4.1--v08.04.01 (Jolly Jellyfi
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Initlialzing PLLs ...done.
InitlialzingClocks ...done.
Initlialzing DDR ...done.
Initializing GTC ...done.
Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Searching for X509 certificate ...not found
Sciclient_pmSetModuleState On, DevId 0x4...
Copying 0x146ac bytes to 0x80000000
Copying 0xb8b4 bytes to 0x800146b0
Copying 0x18c bytes to 0x8001ff64
Copying 0x34 bytes to 0x80020100
Copying 0x34 bytes to 0x80020140
Copying 0x2d78 bytes to 0x80020178
Copying 0x498 bytes to 0x80022ef0
Copying 0x1478 bytes to 0x80023388
Copying 0x4 bytes to 0x80024800
Copying 0x102210 bytes to 0x80735df0
Setting entry point for core 0 @0x80009ef8
Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x80009ef8...
Sciclient_pmSetModuleClkFreq, DevId 0xca @ 2000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0xca...
Sciclient_pmSetModuleState On, DevId 0xca...
Sciclient_pmSetModuleState On, DevId 0xbad0000...
Copying 0xbe0 bytes to 0x70000000
Copying 0x17ac bytes to 0x70008000
Copying 0xdc bytes to 0x700097ac
Copying 0x5e648 bytes to 0x82ccbd00
Copying 0x14 bytes to 0x82d2a348
Copying 0x14 bytes to 0x82d2a35a
Copying 0x34 bytes to 0x82d2a36c
Copying 0x104 bytes to 0x82d2a3a0
Copying 0x28 bytes to 0x82d2a4a4
Copying 0x18 bytes to 0x82d2a4cc
Copying 0x18 bytes to 0x82d2a4e2
Copying 0x28 bytes to 0x82d2a4f8
Copying 0x28 bytes to 0x82d2a51e
Copying 0x24 bytes to 0x82d2a544
Copying 0x28 bytes to 0x82d2a568
Copying 0x24 bytes to 0x82d2a58e
Copying 0x18 bytes to 0x82d2a5b2
Copying 0x18 bytes to 0x82d2a5c8
Copying 0xc4 bytes to 0x82d2a5de
Copying 0x24 bytes to 0x82d2a6a2
Copying 0x24 bytes to 0x82d2a6c6
Copying 0x24 bytes to 0x82d2a6ea
Copying 0x28 bytes to 0x82d2a70e
Copying 0x28 bytes to 0x82d2a736
Copying 0x98 bytes to 0x82d2a75e
Copying 0x20 bytes to 0x82d2a7f8
Copying 0x48 bytes to 0x82d2a818
Copying 0x48 bytes to 0x82d2a860
Copying 0x28 bytes to 0x82d2a8a8
Copying 0x28 bytes to 0x82d2a8d0
Copying 0x1c bytes to 0x82d2a8f8
Copying 0x1c bytes to 0x82d2a912
Copying 0x10 bytes to 0x82d2a92e
Copying 0x28 bytes to 0x82d2a93e
Copying 0x1c bytes to 0x82d2a964
Copying 0x1c bytes to 0x82d2a97e
Copying 0x2c bytes to 0x82d2a99a
Copying 0xe0 bytes to 0x82d2a9c6
Copying 0x18 bytes to 0x82d2aaa6
Copying 0x18 bytes to 0x82d2aabc
Copying 0x28 bytes to 0x82d2aad2
Copying 0xc bytes to 0x82d2aaf8
Copying 0xc bytes to 0x82d2ab04
Copying 0x72a0 bytes to 0x82d2ab10
Copying 0x4 bytes to 0x82d31db0
Copying 0x400 bytes to 0x82d31dc8
Setting entry point for core 4 @0x70000054
Sciclient_procBootSetProcessorCfg, ProcId 0x0, EntryPoint 0x70000054...
Sciclient_procBootSetProcessorCfg...FAILED

     Regards,

    Masaki

  • 0 in reply to Masaki Soga
    TI__Mastermind 42135 points

    Hi Masaki,

    Is this issue still open? 
    If yes, can you please mention the current state of the issue?

    Regards,
    Parth

  • +1 in reply to Parth Nagpal
    Prodigy 70 points
    Parth Nagpal said:
    Can you please share the .out generated at your end and and detailed steps you are using to convert the .out to appimage?

    Hi Parth,

    I have listed the steps above.

    Masaki

  • +1 in reply to Masaki Soga
    TI__Genius 14250 points

    Hi,

    Masaki Soga said:
    I have listed the steps above.

    Is assistance still needed for this thread?

    Regards,

    Karthik