This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3352: Inquiry about bootup-time from de-asserted PWRONRSTn

Part Number: AM3352
Other Parts Discussed in Thread: TPS650250

Hello team,

Our customer is developing the next generation system with AM3352BZCZ60.

Is there a specification/datasheet definition for the time from when PWRONRSTn goes Low->high to  starting to access to the Boot-Device (SPI0)?

As the SPI-Flash’s requirement, there seem to be limitation for this time, and customer would like to confirm it. Customer tried to verify it, and they confirmed this time is around 47usec. Since this requirement is more than 16msec, there is not any problem. If TI has any data/definition for this, would you share this information, please?

It will be appreciated if you will share expert’s advice/comment on this inquiry.

Best regard,

Miyazaki