Hi, I just wanted to confirm that when using the EDMA modes of peripherals with the PSP, that the enableCache configuration setting for most of the peripherals needs to be set to TRUE if the data buffers are in any of the RAMs not in the megamodule (eg SDRAM) . If using a data block from L2 RAM (or L1, if configured that way for that matter), then hw should take care of cache coherency, and this can be set to FALSE for increased performance, correct?
Thanks!
Peter
