TDA4VM: A question about TDA4VM DMA

Hi bingxian,

That's strange, SPI uses completely different DMA channel than TIDL. Typically TIDL uses DRU channels, whereas SPI has its own PDMA channels, so should not conflict. What operations are you doing in SPI? Is it TX or RX or both? Can you please check SPI registers to confirm if it has received or transmitted data? Essentially can you please compare the registers when TIDL is running and when TIDL is not running? Do you see any difference in the registers? 

Also on which cores are you running SPI DMA? Is it on C7x, where TIDL is running? 

Regards,

Brijesh

Hi Brijesh,

1、Our SPI uses TX and RX.

2、By comparison, we find that the registers of MCSPI are invariant when TIDL is running and when TIDL is not running.

Before running TIDL:

After running TIDL:

3、SPI DMA runs on R5F core (MCU1_0)

4、We can only confirm that TIDL has no effect on MCSPI when MCSPI does not use DMA, and that MCSPI will not work when the TIDL program is run while MCSPI uses DMA. DMA channel conflicts are just our guesses.

Regards,

bingxian

Hi bingxian,

One more question, do you see any transfer happening? I want to check if it is just interrupt issue or even transfer not happening? Also if you run SPI in TX only or RX only mode, do you still this issue? 

Regards,

Brijesh

Hi Brijesh,

Because of the complexity of the problem, we did a careful check again,We find that DMA is not the cause of the problem.

We cyclically send the SPI signal at MCU1_0 at a rate of 1ms,When we are not running A72 APP, MCSPI1 sends and receives everything as expected.

Then we run our APP on A72 (avp_master.out), at which point MCU1_0 will print MCSPI1 send error:

We find that this error is SPI busy error.

Our APP(avp_master.out) mainly has functions about TIDL, AVM, coding and decoding. According to our current investigation situation, we cannot know why MCSPI1 is affected by APP.

Regards,

bingxian

update to E2E ticket:

1.Which McSPI instance? MCU_MCSPI0 or MCU_MCSPI1? If not , which MCSPIx in MAIN domain

            MCU1_0 MCSPI1.

2.Is it MASTER or SLAVE mode on TDA4VM side for McSPI?

           is MASTER .

3.TX only mode or RX only mode?

           TX and RX both mode.

4.is there any relationship between McSPI communication and TIDL algorithm? For example, data conveyed on McSPI connection need be sent to TIDL algorithm?

           MCSPI1 is not associated with TIDL.

5.Is it possible to scale down your use case to a small one then it can run on TDA4VM EVM?

           Our use case involves a camera for our own use, etc., so cannot currently run on the tda4vm evm

Hi bingxian,

It seems you are using SPI driver from MCAL, because i dont see this API Spi_AsyncTransmit in PDK SPI driver. Please confirm.

What is SPI busy error? can you please go inside this function using CCS + JTAG and see where it is returning error? 

Regards,

Brijesh

Hi Brijesh,

We are using the driver from MCAL.

The MCAL SPI.c function Spi_GetSequenceResult returns a value sometimes SPI_SEQ_PENDING, which causes an SPI transfer error.

Spi_GetSequenceResult always returns SPI_SEQ_OK when A72 is not running app(avp_master.out).

Spi_GetSequenceResult sometimes returns SPI_SEQ_PENDING after running app(avp_master.out)

The Spi_GetSequenceResult function is as follows:

Regards,

bingxian

Hi bingxian,

Sorry, not much familiar with the MCAL driver, can you please check where seqResult variable is set? 

Regards,

Brijesh

Hi Brijesh,

The seqResult variable is set to SPI_SEQ_OK only when initialized and when the SPI DMA sends an interrupt.

We feel that after running the app(avp_master.out), the SPI DMA interrupt is sometimes not generated

Hi Brijesh,

Hello,

Can you please share the register dump for the below when its working vs not working ? 

0x04301C0B0
0x04301C0B4
0x04301C0B8
0x04301C0BC
0x04301C044 & 0x04301C0E4
0x04301C048 & 0x04301C0EC
0x04301C0C4

0x040F04060

Which chip select are you using ?

Regards

Tarun Mukesh

Hi Tarun Mukesh,

1.The values of these registers before app(avp_master.out) are as follows:

2.After app(avp_master.out) runs, these registers have the following values:

3.Our chip is XJ721EGALF

Regards,

bingxian

Can please confirm the differences which you shared are under conditions (running McSPI on MCU R5) vs (running McSPI on MCUR5 + App on A72) ?

bingxian lu said:

Spi_GetSequenceResult sometimes returns SPI_SEQ_PENDING after running app(avp_master.out)

Are the point 2 values of pending case or working case ?

Regards

Tarun Mukesh

Hi Tarun Mukesh,

Did you confirm the return value of Spi_GetSequenceResult before and after APP running of A72?

The period for our MCSPI1 to send data is 1ms.

Spi_GetSequenceResult always returns SPI_SEQ_OK when APP (avp_master.out) is not running.

After the APP runs, Spi_GetSequenceResult will return SPI_SEQ_PENDING once in about 2S, causing MCSPI1 to fail to transfer.

Regards,

bingxian

Hello,

bingxian lu said:

Did you confirm the return value of Spi_GetSequenceResult before and after APP running of A72?

What exactly you want me to confirm ? 

In Spi_Dma.c , Under Spi_DmaRegisterEvent() API for DMA completion can you make eventMode from UDMA_EVENT_MODE_SHARED to UDMA_EVENT_MODE_EXCLUSIVE for both Tx and Rx.

Can you check whether you are facing similar after doing the change ?

And also can you ensure the application(avp_master.out)) running on A72 is not using MCU_SPI1 ?

Regards

Tarun Mukesh

Hi Tarun Mukesh,

Tarun Mukesh Puvvada said:

Can you check whether you are facing similar after doing the change ?

I made the modification according to your requirements, but I still face the same problem as the original one after the modification.

Tarun Mukesh Puvvada said:

And also can you ensure the application(avp_master.out)) running on A72 is not using MCU_SPI1 ?

The APP of A72 does not use MCSPI1

 I tried to turn off the DMA of MCSPI1 and found that MCSPI1 works fine after running the APP(avp_master.out) on the A72.

Regards,

bingxian

Hi bingxian,

Is your application using any DMA channel from MCU domain? If not, that's surprising that it works after application is started. 

Regards,

Brijesh

Hi Brijesh,

Brijesh Jadav said:

Is your application using any DMA channel from MCU domain?

Our app on the A72 also does not use the DMA channel to the MCU domain.

According to the manual, MCU_PDMA1 only serve MCSPI1 and MCSPI2, the problem we have should not be a problem with DMA being occupied.

Regards,

bingxian

Hello,

Thanks for sharing the logs as requested.

bingxian lu said:

By comparison, we find that the registers of MCSPI are invariant when TIDL is running and when TIDL is not running.

I have looked into the log of registers which you have shared earlier, MCSPI_MODULCTRL=0x4 in both the cases.

Which indicates it is in Slave Mode.

bingxian lu said:

.Is it MASTER or SLAVE mode on TDA4VM side for McSPI?

           is MASTER .

But you have mentioned it to be in Master Mode.MCAL driver supports only Master mode.

And also all the Tx and Rx registers are no showing no data transfer.

Kindly request to share the register dump exactly at point when McSPI- DMA is working(transferring data) vs McSPI-DMA + APP not working.

Regards

Tarun Mukesh

Hi Tarun Mukesh,

Sorry, I read the wrong register before.

MCU_MCSPI1 correct register status is as follows：

Before running the A72 app:

After running the A72 app:

Regards,

bingxian

Hello Bingxian,

We are looking into the issue thoroughly and trying to narrow down the possible deviations. 

In Udma_chEnableLocal() API ,can you please keep a break point at 

CSL_udmapSetTxRT(&drvHandle->udmapRegs, chHandle->txChNum, &udmapRtEnable);

and share me the details of txChNum value ?

Regards

Tarun Mukesh

Hi Tarun Mukesh,

txChNum has a value of 30

Regards,

bingxian

Hello,

As the txChNum =30 , Can you please share me the register dump at 0x2AA1E000 location during non working(failed) scenario?

Regards

Tarun Mukesh

Hi Tarun Mukesh,

I print out the register value when MCU_MCSPI1 transmission error with a value of 0x00.

Since it is not easy to get incorrect results when debugging with CCS, we can only print out the register value when there is an error.

Regards,

bingxian

Hello Bingxian,

Thanks for sharing ,from the above we are able to understand UDMA channel is not getting enabled.

when McSPI is unable to transmit and during this hung condition then can you connect CCS and see register dump at 0x2AA1E000 value is same as you sent .if it the same can you make 0x2AA1E000 = 0x80000000 (Set the 31st bit )

and then see McSPI able to transmit 

Regards

Tarun Mukesh

Hi Tarun Mukesh,

1.I can't find a description of the register 0x2AA1E000 in the data sheet, what kind of register is this register?

2.I set bit 31 of this register to 1 before sending, but I still get an SPI transmission error.

3.We also found a situation: after we changed the MCU_MCSPI1 transmission period from 1ms to 10ms MCU_MCSPI1 no transmission error was reported.

Regards,

bingxian

Hello,

The register is from the picture above,as you are using channel 30 the offset is calculated and 0x2AA1E000 is the address.

The UDMA channel is not getting enabled ,once it enables then only we can have previous data transmit changes from pending to done and starts new data transmission.

Please use CCS tool to write the value into the register .When you are facing the failed scenario connect CCS and write the value provided into the location.

Regards

Tarun Mukesh

Hi Tarun Mukesh,

I use CCS to put a breakpoint on the MCU_MCSPI1 transmission error, and I write 1 on bit 31 of the register 0x2AA1E000 when there is a transmission error. But I observed with an oscilloscope MCU_MCSPI1_CLK there was no waveform output.

I also tried calling the write register function on SPI transmission error HW_WR_REG32_RAW writing 31 bits of register 0x2AA1E000 to 1, but I observed that MCU_MCSPI1_CLK also had no waveform output.

Regards,

bingxian

Hi Tarun Mukesh,

Thank you for your patience, we troubleshooted the problem and solved the problem.

Regards,

bingxian

Hi Binaxian,

Can you please some more information as to what was the issue? Was it somewhere in the released SDK ? 

Regards,

Brijesh

Hi Tarun Mukesh,

Thank you again for your patient reply to us.

The SDK is fine, there is a problem with our own configuration.

Regards,

bingxian