C6455 srio register settings are inconsistent?

Erik Zhang

Hi,

We have a master C6455 connected to other three C6455s via three 1x srio connections. The dsps' RIOCLKs are distributed by lvds distributor with the same osillator at 125Mhz. The line rate is 1.25ghz with 4 port 1x mode. We modifed the CSL code and the initializations are Ok.

We have checked the register as follows:

PER_SET_CNTL = 0x14F(1X_MODE=1)

SP_IP_MODE = 0x4400003F(SP_MODE=01)

SERDES_CFG0_CNTL= 0xB (MPY=10x)

SERDES_CFGRX0_CNTL = 0x81121 (Half rate)

SERDES_CFGTX0_CNTL = 0x10821

But when we used srio_write(NWrite) to write data from mater dsp to slave, the SP0_ERR_STAT changed to 0x30002. So we checked those registers setting again, they were the same. We checked more registers and found that SP0_CTL = 0x4xxx_xxxx and SP1/2/3_CTL is the same value. That means this is a Four-lane port. Does it conflict with the registers above?

One more question is: Could it be caused by unlocked srio clock? Should we check whether the srio clock is locked or not?

over 14 years ago

0 tscheck over 14 years ago

TI__Mastermind 23525 points

Erik,

If port_ok is set, it means the link partners are successfully exchanging idles and control symbols, which is good. I don't think it is related to the clock, the fact that all devices are using the same reference is a plus to. Your multiply settings are correct, but I did notice that you don't have the TX raised common mode set, which is needed if you are using AC coupling. Here are the settings for the registers that we use for your configuration in our boot ROM:

PER_SET_CNTL = 0x05053750

SP_IP_MODE = 0x4C000000

SERDES_CFG0_CNTL= 0x0000000B

SERDES_CFGRX0_CNTL = 0x00081121

SERDES_CFGTX0_CNTL = 0x00010921

It is possible to be in port_ok, but also be in a input or output error stopped state. You are indicating a output error stopped state in the sp0_err_stat. You need to clear error states before trying to send data packets. Please look at appendix B of: http://focus.ti.com/lit/ug/spru976e/spru976e.pdf

Look at the srio_init.c file and solution I posted here: http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/33378/119907.aspx#119907 the sequence is important when writing to the registers.

Also, check out the following thread: http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/97140/359057.aspx#359057 for some ideas on things to look at.

Basically, I think you just need to get out of the error state.

Regards,

Travis

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C6455 srio register settings are inconsistent?