Need to clarify something in the bootloader document
1. The bootloader is DSP code (stored inside internal L3 ROM 128 KB that starts at 0x20B00000?) that transfer application code (instruction code and not data?) from slow non-volatile external memory (external ROM?? in the case of EMIF boot option) into high-speed internal memory (DDR3 SDRAM??)
2. What do you mean by "Boot is driven on a device reset by CorePac0" on pg 2-2.
3. What is PORz pin (or RESETFULLz)? Isn't it just POR pin on the C66 chip? Or is it every DSP core has its own POR pin?