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AM5726: TMS320C66 MMU configuration

Rasty Slutsker
Expert 1830 points
Part Number: AM5726
Other Parts Discussed in Thread: SYSBIOS

Hi guys

Quick question.

Can you give me a pointer to place (source file, cfg, else) where MMU of TMS320C66x (AM572x) are set up, particularly cached and non-cached areas?

Best regard

Rasty 

  • 0
    Expert 1830 points

    Hi

    I'd like to understand where cache configuration takes place. 

    Where do you set that DDR is cached, while GPMC and OnChip RAM are not?

    Best regards

    Rasty

  • 0 in reply to Rasty Slutsker
    TI__Guru** 113475 points

    Hi Rasty,

    The DSP subsystems on AM57xx devices have two MMUs as you have noted in your diagram. The first MMU0 is for the DSP processor itself, while the second MMU1 is for the EDMA engine within the subsystem. If using MMUs (Linux on A15 uses the MMUs), the recommendation is to program both the MMUs identically. These MMUs only provide the address translation, but do not dictate the Cache properties like one might expect with regular processors.

    There is no separate Cache space on the DSPs, and instead the DSP L1 and L2 memories can be partitioned between SRAM and/or Cache. The DSP Caches are all explained in a separate TMS320C66x DSP Cache User Guide ( SPRUGY8) document as pointed out in the 5.3.2.1 C66x DSP Subsystem Introduction section of the AM57xx TRMs.

    The Cache configuration on DSPs are managed through the MAR Registers that can set the properties with a granularity of 16 MB regions. This is managed through the TI SYS/BIOS Cache module in s/w. Please see the appropriate SYS/BIOS version's documentation. Following is the reference from SYS/BIOS 6.83.00.18 Cache module.

    You can see the references in existing IPC examples or other application examples in the SDK, the configuration is usually done in the associated application's .cfg file.

    regards

    Suman

  • 0 in reply to Suman Anna
    Expert 1830 points

    Hi,

    Than you for the links.

    I do not find anything (cfg) with cache configuration example for c6x.

    Can you attach example?

    Best regards

    Rasty

  • 0 in reply to Suman Anna
    Expert 1830 points

    I scanned all TI source tree for cfg files that include line "var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');"

    I found only:

    /* make SR_0 non-cacheable */
    var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
    Cache.setMarMeta(ipc_cfg.SR0Mem.base, ipc_cfg.SR0Mem.len, Cache.Mar_DISABLE);

    Where do you set that other regions are cached? 

    Can you help me an example of cfg that defines cached and non-cached areas?

  • +1 in reply to Rasty Slutsker
    TI__Guru 50045 points

    Here is some example configuration for your reference. 

    The syntax used in cfg file for cache can be found at ~/bios_6_46_06_00/docs/cdoc/ti/sysbios/family/c66/Cache.html.

    /* Invoke Cache module in SYSBIOS */
    var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
    /* Program Cache size */
    Cache.initSize.l1pSize = Cache.L1Size_32K;
    Cache.initSize.l1dSize = Cache.L1Size_32K;
    Cache.initSize.l2Size  = Cache.L2Size_32K;

    /* Configure MARs, by default cache is enabled for the entire memory region defined in linker command file */
    for (var i = 0; i < Program.cpu.memoryMap.length; i++)
    {
       memSegment = Program.cpu.memoryMap[i];
       {
       Cache.setMarMeta(memSegment.base, memSegment.len, Cache.Mar_ENABLE | Cache.PFX);
       }
    }
             /* Certain memory region can be configured as non-cached region, for example, if the memory segment is named as SR0 intended for IPC */
    for (var i = 0; i < Program.cpu.memoryMap.length; i++)
    {
      memSegment = Program.cpu.memoryMap[i];

      if ((memSegment.name == "SR0")
         {
            Cache.setMarMeta(memSegment.base, memSegment.len, Cache.Mar_DISABLE);
         }
    }

    The above configuration will program the below MARn registers to enable/disable DSP cacheability.

    Please refer to C66x CPU spec for details.

    https://www.ti.com/lit/ug/sprugw0c/sprugw0c.pdf

    Regards,

    Stanley

  • 0 in reply to Stanley Liu
    Expert 1830 points

    Thank you very much for example.

    Can you show me where in stock example you configure ddr cache (cashed) and internal memory cache (not cached).

  • 0 in reply to Rasty Slutsker
    TI__Guru 50045 points

    The example code I shared is not from AM57x SDK. 

    I took it from another SDK for similar processor TDA2x with same C66x DSP.

    https://www.ti.com/tool/PROCESSOR-SDK-TDAX

    In any case, the way to configure in SYSBIOS is the same based on SYSBIOS API reference guide.

    Regards,
    Stanley

  • 0 in reply to Stanley Liu
    Expert 1830 points

    Hi,

    I found this module ti.sysbios.family.c66.Cache , but it does not contain examples.

    I'd like to understand how Program.cpu.memoryMap gets populated 

    Can you submit whole cfg file?

    Best regards

    Rasty

  • 0 in reply to Rasty Slutsker
    TI__Guru 50045 points

    Had review session with Rasty and team and clarified the questions. Will close this thread.